From 8b66b8eb9c8318b506aeb3e53d9d16006b700a4c Mon Sep 17 00:00:00 2001
From: occheung <dc@m-labs.hk>
Date: Fri, 21 Aug 2020 11:17:08 +0800
Subject: [PATCH] migen: fix lvds input

---
 migen/fpga_config.py | 58 ++++++++++++++++++++++++++++++++------------
 shell.nix            |  1 +
 2 files changed, 44 insertions(+), 15 deletions(-)

diff --git a/migen/fpga_config.py b/migen/fpga_config.py
index db4825d..58afa74 100644
--- a/migen/fpga_config.py
+++ b/migen/fpga_config.py
@@ -1,47 +1,75 @@
 from humpback import HumpbackPlatform
 from migen.fhdl.module import Module
+from migen.fhdl.specials import Instance
+from migen.fhdl.bitcontainer import value_bits_sign
+from migen.genlib.io import *
+from migen.build.lattice.common import LatticeiCE40DifferentialInputImpl
+from migen.genlib.io import DifferentialInput
+
 
 class UrukulConnector(Module):
 	def __init__(self, platform):
 		# Request EEM I/O & SPI
-		eem = platform.request("eem", 0)
+#		eem = platform.request("eem", 0)
+		eem0 = platform.request("eem0", 0);
+		eem1 = platform.request("eem0", 1);
+#		eem2 = platform.request("eem0", 2);
+		eem2 = platform.request("eem0_n", 2);
+#		_ignore_eem2 = platform.request("eem0_n", 2);
+#		miso = platform.request("miso", 0);
+		eem3 = platform.request("eem0", 3);
+		eem4 = platform.request("eem0", 4);
+		eem5 = platform.request("eem0", 5);
 		spi = platform.request("spi")
 		led = platform.request("user_led")
 
 		# Assert signal length
-		assert len(eem.p) == 8
-		assert len(eem.n) == 8
+		# TODO: Refactor assertion
 		assert len(spi.sclk) == 1
 		assert len(spi.mosi) == 1
-		assert len(spi.miso) == 1
+#		assert len(spi.miso) == 1
 		assert len(spi.cs) == 3
 
 		# Flip positive signal as negative output, maybe only do it for FPGA outputs
 		# self.comb += eem.n.eq(~eem.p)
+		self.sdo = Signal()
+
+		self.specials += Instance("SB_IO",
+							p_PIN_TYPE=C(0b000001, 6),
+							p_IO_STANDARD="SB_LVDS_INPUT",
+							io_PACKAGE_PIN=eem2,
+							i_D_OUT_0=self.sdo,
+							o_D_IN_0=spi.miso
+						)
+
+#		self.submodules += LatticeiCE40DifferentialInputImpl(eem2.p, eem2.n, spi.miso)
+#		self.specials += DifferentialInput(eem2, None, spi.miso)
 
 		# Link EEM to SPI
 		self.comb += [
 
-			eem.p[0].eq(spi.sclk),
-			eem.n[0].eq(~spi.sclk),
+			eem0.p.eq(spi.sclk),
+			eem0.n.eq(~spi.sclk),
 
-			eem.p[1].eq(spi.mosi),
-			eem.n[1].eq(~spi.mosi),
+			eem1.p.eq(spi.mosi),
+			eem1.n.eq(~spi.mosi),
 
-			spi.miso.eq(eem.p[2]),
+#			spi.miso.eq(eem2.p),
 
-			eem.p[3].eq(spi.cs[0]),
-			eem.n[3].eq(~spi.cs[0]),
+			eem3.p.eq(spi.cs[0]),
+			eem3.n.eq(~spi.cs[0]),
 
-			eem.p[4].eq(spi.cs[1]),
-			eem.n[4].eq(~spi.cs[1]),
+			eem4.p.eq(spi.cs[1]),
+			eem4.n.eq(~spi.cs[1]),
 
-			eem.p[5].eq(spi.cs[2]),
-			eem.n[5].eq(~spi.cs[2]),
+			eem5.p.eq(spi.cs[2]),
+			eem5.n.eq(~spi.cs[2]),
 
 			led.eq(1)
 		]
 
+
+
 		# Debug purposes: Tie EEM MISO to EEM MOSI
 		# self.comb += eem.p[2].eq(eem.p[1])
 
diff --git a/shell.nix b/shell.nix
index 91b2954..a221d56 100644
--- a/shell.nix
+++ b/shell.nix
@@ -72,6 +72,7 @@ in
 			(pkgs.python3.withPackages(ps: [ migen ]))
 			pkgs.yosys
 			pkgs.nextpnr
+			pkgs.arachne-pnr
 			pkgs.icestorm
 			pkgs.gdb
 			openocd