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urukul: add master clock div getter

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This commit is contained in:
occheung 2020-09-23 12:33:22 +08:00
parent c0e0c381ec
commit 2ef6bb393c
2 changed files with 10 additions and 2 deletions
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1
src/config_register.rs
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@ -75,7 +75,6 @@ where
/*
* Return selected configuration field
* TODO: Return result type instead for error checking
*/
pub fn get_configuration(&mut self, config_type: CFGMask) -> u8 {
config_type.get_filtered_content(self.data) as u8

11
src/lib.rs
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@ -231,7 +231,7 @@ where
fn set_dds_ref_clk(&mut self) -> Result<(), Error<E>> {
// Calculate reference clock frequency after clock division from configuration register
let f_ref_clk = self.f_master_clk / (self.config_register.get_configuration(CFGMask::DIV) as f64);
let f_ref_clk = self.f_master_clk / (self.get_master_clock_division() as f64);
// Update all DDS chips on reference clock frequency
for dds_channel in 0..4 {
@ -240,6 +240,15 @@ where
Ok(())
}
fn get_master_clock_division(&mut self) -> u8 {
match self.config_register.get_configuration(CFGMask::DIV) {
0 | 3 => 4,
1 => 1,
2 => 2,
_ => panic!("Divisor out of range, when reading configuration register (CPLD)."),
}
}
fn set_channel_attenuation(&mut self, channel: u8, attenuation: f32) -> Result<(), Error<E>> {
if channel >= 4 || attenuation < 0.0 || attenuation > 31.5 {
return Err(Error::ParameterError);