forked from M-Labs/humpback-dds
migen: fix lvds polarity
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8b66b8eb9c
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2d7302bdca
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@ -32,6 +32,7 @@ class UrukulConnector(Module):
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# Flip positive signal as negative output, maybe only do it for FPGA outputs
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# Flip positive signal as negative output, maybe only do it for FPGA outputs
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# self.comb += eem.n.eq(~eem.p)
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# self.comb += eem.n.eq(~eem.p)
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self.miso_n = Signal()
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self.sdo = Signal()
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self.sdo = Signal()
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self.specials += Instance("SB_IO",
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self.specials += Instance("SB_IO",
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@ -39,7 +40,7 @@ class UrukulConnector(Module):
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p_IO_STANDARD="SB_LVDS_INPUT",
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p_IO_STANDARD="SB_LVDS_INPUT",
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io_PACKAGE_PIN=eem2,
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io_PACKAGE_PIN=eem2,
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i_D_OUT_0=self.sdo,
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i_D_OUT_0=self.sdo,
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o_D_IN_0=spi.miso
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o_D_IN_0=self.miso_n
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)
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)
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# self.submodules += LatticeiCE40DifferentialInputImpl(eem2.p, eem2.n, spi.miso)
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# self.submodules += LatticeiCE40DifferentialInputImpl(eem2.p, eem2.n, spi.miso)
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@ -55,6 +56,7 @@ class UrukulConnector(Module):
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eem1.n.eq(~spi.mosi),
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eem1.n.eq(~spi.mosi),
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# spi.miso.eq(eem2.p),
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# spi.miso.eq(eem2.p),
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spi.miso.eq(~self.miso_n),
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eem3.p.eq(spi.cs[0]),
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eem3.p.eq(spi.cs[0]),
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eem3.n.eq(~spi.cs[0]),
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eem3.n.eq(~spi.cs[0]),
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