From 2d7302bdca272f48cef79fdbc992ee8353cd969a Mon Sep 17 00:00:00 2001
From: occheung <dc@m-labs.hk>
Date: Fri, 21 Aug 2020 11:36:16 +0800
Subject: [PATCH] migen: fix lvds polarity

---
 migen/fpga_config.py | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/migen/fpga_config.py b/migen/fpga_config.py
index 58afa74..e36cb8d 100644
--- a/migen/fpga_config.py
+++ b/migen/fpga_config.py
@@ -32,6 +32,7 @@ class UrukulConnector(Module):
 
 		# Flip positive signal as negative output, maybe only do it for FPGA outputs
 		# self.comb += eem.n.eq(~eem.p)
+		self.miso_n = Signal()
 		self.sdo = Signal()
 
 		self.specials += Instance("SB_IO",
@@ -39,7 +40,7 @@ class UrukulConnector(Module):
 							p_IO_STANDARD="SB_LVDS_INPUT",
 							io_PACKAGE_PIN=eem2,
 							i_D_OUT_0=self.sdo,
-							o_D_IN_0=spi.miso
+							o_D_IN_0=self.miso_n
 						)
 
 #		self.submodules += LatticeiCE40DifferentialInputImpl(eem2.p, eem2.n, spi.miso)
@@ -55,6 +56,7 @@ class UrukulConnector(Module):
 			eem1.n.eq(~spi.mosi),
 
 #			spi.miso.eq(eem2.p),
+			spi.miso.eq(~self.miso_n),
 
 			eem3.p.eq(spi.cs[0]),
 			eem3.n.eq(~spi.cs[0]),