CPLD/FPGA gateware on Urukul. Forked from https://github.com/quartiq/urukul
Updated 2025-04-11 10:57:28 +08:00
Updated 2025-02-08 12:58:21 +08:00
Simple netboot tool compatible with ARTIQ/MiSoC and SZL bootloaders
Updated 2025-02-08 12:58:20 +08:00
Formally verified ARTIQ RTIO core in nMigen
Updated 2025-02-08 12:58:20 +08:00
Updated 2025-02-08 12:58:20 +08:00
A port of [riscv-formal](https://github.com/SymbioticEDA/riscv-formal) to nMigen
Updated 2025-02-08 12:58:20 +08:00
Minimalist bare metal Rust firmware for Red Pitaya
Updated 2025-02-08 12:58:20 +08:00