86 lines
1.5 KiB
Rust
86 lines
1.5 KiB
Rust
#![no_std]
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#![no_main]
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#![feature(asm)]
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#![feature(naked_functions)]
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use core::fmt::Write;
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use panic_abort as _;
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use r0::zero_bss;
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mod regs;
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mod cortex_a9;
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mod slcr;
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mod uart;
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use uart::Uart;
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mod eth;
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use crate::cortex_a9::{asm, regs::*};
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extern "C" {
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static mut __bss_start: u32;
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static mut __bss_end: u32;
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static mut __end: u32;
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}
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#[link_section = ".text.boot"]
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#[no_mangle]
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#[naked]
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pub unsafe extern "C" fn _boot_cores() -> ! {
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const CORE_MASK: u32 = 0x3;
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let stack_start = __end + 4096;
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match MPIDR.get() & CORE_MASK {
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0 => {
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SP.set(stack_start);
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boot_core0();
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}
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_ => loop {
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// if not core0, infinitely wait for events
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asm::wfe();
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},
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}
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}
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unsafe fn boot_core0() -> ! {
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l1_cache_init();
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zero_bss(&mut __bss_start, &mut __bss_end);
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main();
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panic!("return from main");
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}
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fn l1_cache_init() {
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// Invalidate TLBs
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tlbiall();
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// Invalidate I-Cache
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iciallu();
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// Invalidate Branch Predictor Array
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bpiall();
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// Invalidate D-Cache
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dccisw();
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// (Initialize MMU)
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// Enable I-Cache and D-Cache
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sctlr();
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// Synchronization barriers
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// Allows MMU to start
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asm::dsb();
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// Flushes pre-fetch buffer
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asm::isb();
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}
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fn main() {
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let mut uart = Uart::serial(115_200);
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loop {
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for i in 0.. {
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writeln!(uart, "i={}\r", i);
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}
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}
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let eth = eth::Eth::gem0();
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loop {
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}
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}
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