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Bare-metal Rust on Zynq-7000
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pca006132 0efc7a616f libconfig: implemented config write 
Config write and config remove are now implemented.
Config keys are now treated case insensitively, which is consistence to
the filesystem behavior.
BOOT.BIN can be replaced by setting the config key "boot".
 		2020-10-30 16:11:18 +08:00
.cargo cargo: remove unmaintained runner 2020-09-09 15:01:39 +08:00
experiments experiments: fix zc706 build 2020-09-09 21:30:56 +08:00
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libcoreio add libconfig, libcoreio, szl from artiq-zynq a277e89b3ad; update dependencies 2020-09-09 17:56:50 +08:00
libcortex_a9 add Red Pitaya support (WIP) 2020-09-09 20:10:05 +08:00
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README.md README: add introduction 2020-09-29 16:27:44 +08:00
armv7-none-eabihf.json define custom target, use with cargo-xbuild 2019-08-06 22:03:04 +02:00
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README.md

Bare-metal Rust on Zynq-7000

Supported features:

  • Clocking setup
  • UART
  • SDRAM setup
  • Ethernet with smoltcp and async-await on TCP sockets
  • SD card
  • PL programming and startup
  • Pure Rust SZL first-stage bootloader, with SD boot and netboot
  • Control of second CPU core and message passing, with async-await support

Supported boards:

  • ZC706
  • Red Pitaya (note: SDRAM issues, worked around using ps7_init)
  • Cora Z7-10 (note: SDRAM issues)

Build

nix-shell --command "cargo xbuild --release -p experiments"

Currently the ELF output is placed at target/armv7-none-eabihf/release/experiments

Debug

Running on the ZC706

nix-shell --command "cargo xbuild --release -p experiments"
cd openocd
openocd -f zc706.cfg

Running on the Cora Z7-10

nix-shell --command "cd experiments && cargo xbuild --release --no-default-features --features=target_cora_z7_10"
cd openocd
openocd -f cora-z7-10.cfg

Loading a bitstream into volatile memory

openocd -f zc706.cfg -c "pld load 0 blinker_migen.bit; exit"