333 lines
9.5 KiB
Rust
333 lines
9.5 KiB
Rust
//! I2C Bit-banging Controller
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mod regs;
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pub mod eeprom;
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use super::slcr;
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use super::time::Microseconds;
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use embedded_hal::timer::CountDown;
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use libregister::{RegisterR, RegisterRW, RegisterW};
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#[cfg(feature = "target_kasli_soc")]
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use log::info;
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pub enum I2cMultiplexer {
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PCA9548 = 0,
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#[cfg(feature = "target_kasli_soc")]
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PCA9547 = 1,
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}
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pub struct I2c {
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regs: regs::RegisterBlock,
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count_down: super::timer::global::CountDown<Microseconds>,
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pca_type: I2cMultiplexer
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}
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impl I2c {
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#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
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pub fn i2c0() -> Self {
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// Route I2C 0 SCL / SDA Signals to MIO Pins 50 / 51
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slcr::RegisterBlock::unlocked(|slcr| {
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// SCL
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slcr.mio_pin_50.write(
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slcr::MioPin50::zeroed()
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.l3_sel(0b000) // as GPIO 50
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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.disable_rcvr(true)
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);
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// SDA
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slcr.mio_pin_51.write(
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slcr::MioPin51::zeroed()
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.l3_sel(0b000) // as GPIO 51
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.io_type(slcr::IoBufferType::Lvcmos18)
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.pullup(true)
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.disable_rcvr(true)
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);
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// On Kasli-SoC prototype, leakage through the unconfigured I2C_SW_RESET
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// MIO pin develops enough voltage on the T21 gate to assert the reset.
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// Configure the pin to avoid this problem.
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#[cfg(feature = "target_kasli_soc")]
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slcr.mio_pin_33.write(
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slcr::MioPin33::zeroed()
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.l3_sel(0b000)
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.io_type(slcr::IoBufferType::Lvcmos33)
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.pullup(false)
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.disable_rcvr(true)
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);
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});
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Self::i2c_common(0xFFFF - 0x000C, 0xFFFF - 0x0002)
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}
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fn i2c_common(gpio_output_mask: u16, _gpio_output_mask_lower: u16) -> Self {
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// Setup register block
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let self_ = Self {
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regs: regs::RegisterBlock::i2c(),
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count_down: unsafe { super::timer::GlobalTimer::get() }.countdown(),
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pca_type: I2cMultiplexer::PCA9548 //default for zc706
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};
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// Setup GPIO output mask
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self_.regs.gpio_output_mask.modify(|_, w| {
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w.mask(gpio_output_mask)
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});
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// Setup GPIO driver direction
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self_.regs.gpio_direction.modify(|_, w| {
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w.scl(true).sda(true)
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});
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//Kasli-SoC only: I2C_SW_RESET configuration
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#[cfg(feature = "target_kasli_soc")]
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{
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self_.regs.gpio_output_mask_lower.modify(|_, w| {
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w.mask(_gpio_output_mask_lower)
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});
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self_.regs.gpio_direction.modify(|_, w| {
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w.i2cswr(true)
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});
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}
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self_
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}
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/// Delay for I2C operations, simple wrapper for nb.
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fn delay_us(&mut self, us: u64) {
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self.count_down.start(Microseconds(us));
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nb::block!(self.count_down.wait()).unwrap();
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}
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fn unit_delay(&mut self) { self.delay_us(100) }
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fn sda_i(&mut self) -> bool {
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self.regs.gpio_input.read().sda()
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}
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fn scl_i(&mut self) -> bool {
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self.regs.gpio_input.read().scl()
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}
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fn sda_oe(&mut self, oe: bool) {
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self.regs.gpio_output_enable.modify(|_, w| {
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w.sda(oe)
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})
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}
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fn sda_o(&mut self, o: bool) {
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self.regs.gpio_output_mask.modify(|_, w| {
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w.sda_o(o)
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})
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}
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fn scl_oe(&mut self, oe: bool) {
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self.regs.gpio_output_enable.modify(|_, w| {
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w.scl(oe)
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})
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}
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fn scl_o(&mut self, o: bool) {
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self.regs.gpio_output_mask.modify(|_, w| {
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w.scl_o(o)
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})
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}
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#[cfg(feature = "target_kasli_soc")]
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fn i2cswr_oe(&mut self, oe: bool) {
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self.regs.gpio_output_enable.modify(|_, w| {
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w.i2cswr(oe)
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})
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}
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#[cfg(feature = "target_kasli_soc")]
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fn i2cswr_o(&mut self, o: bool) {
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self.regs.gpio_output_mask_lower.modify(|_, w| {
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w.i2cswr_o(o)
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})
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}
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#[cfg(feature = "target_kasli_soc")]
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fn pca_autodetect(&mut self) -> Result<I2cMultiplexer, &'static str> {
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// start with resetting the PCA954X
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// SDA must be clear (before start)
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// reset time is 500ns, unit_delay (100us) to account for propagation
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self.i2cswr_o(true);
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self.unit_delay();
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self.i2cswr_o(false);
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self.unit_delay();
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let pca954x_read_addr = (0x71 << 1) | 0x01;
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self.start()?;
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// read the config register
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if !self.write(pca954x_read_addr)? {
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return Err("PCA954X failed to ack read address");
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}
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let config = self.read(false)?;
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let pca = match config {
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0x00 => { info!("PCA9548 detected"); I2cMultiplexer::PCA9548 },
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0x08 => { info!("PCA9547 detected"); I2cMultiplexer::PCA9547 },
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_ => { return Err("Unknown response for PCA954X autodetect")},
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};
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self.stop()?;
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Ok(pca)
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}
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pub fn init(&mut self) -> Result<(), &'static str> {
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self.scl_oe(false);
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self.sda_oe(false);
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self.scl_o(false);
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self.sda_o(false);
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// Check the I2C bus is ready
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self.unit_delay();
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self.unit_delay();
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if !self.sda_i() {
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// Try toggling SCL a few times
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for _bit in 0..8 {
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self.scl_oe(true);
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self.unit_delay();
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self.scl_oe(false);
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self.unit_delay();
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}
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}
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if !self.sda_i() {
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return Err("SDA is stuck low and doesn't get unstuck");
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}
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if !self.scl_i() {
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return Err("SCL is stuck low");
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}
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// postcondition: SCL and SDA high
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#[cfg(feature = "target_kasli_soc")]
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{
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self.i2cswr_oe(true);
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self.pca_type = self.pca_autodetect()?;
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}
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Ok(())
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}
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pub fn start(&mut self) -> Result<(), &'static str> {
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// precondition: SCL and SDA high
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if !self.scl_i() {
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return Err("SCL is stuck low");
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}
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if !self.sda_i() {
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return Err("SDA arbitration lost");
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}
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self.sda_oe(true);
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self.unit_delay();
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self.scl_oe(true);
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self.unit_delay();
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// postcondition: SCL and SDA low
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Ok(())
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}
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pub fn restart(&mut self) -> Result<(), &'static str> {
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// precondition SCL and SDA low
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self.sda_oe(false);
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self.unit_delay();
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self.scl_oe(false);
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self.unit_delay();
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self.start()?;
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// postcondition: SCL and SDA low
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Ok(())
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}
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pub fn stop(&mut self) -> Result<(), &'static str> {
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// precondition: SCL and SDA low
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self.unit_delay();
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self.scl_oe(false);
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self.unit_delay();
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self.sda_oe(false);
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self.unit_delay();
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if !self.sda_i() {
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return Err("SDA arbitration lost");
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}
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// postcondition: SCL and SDA high
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Ok(())
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}
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pub fn write(&mut self, data: u8) -> Result<bool, &'static str> {
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// precondition: SCL and SDA low
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// MSB first
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for bit in (0..8).rev() {
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self.sda_oe(data & (1 << bit) == 0);
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self.unit_delay();
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self.scl_oe(false);
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self.unit_delay();
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self.scl_oe(true);
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self.unit_delay();
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}
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self.sda_oe(false);
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self.unit_delay();
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self.scl_oe(false);
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self.unit_delay();
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// Read ack/nack
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let ack = !self.sda_i();
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self.scl_oe(true);
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self.unit_delay();
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self.sda_oe(true);
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// postcondition: SCL and SDA low
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Ok(ack)
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}
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pub fn read(&mut self, ack: bool) -> Result<u8, &'static str> {
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// precondition: SCL and SDA low
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self.sda_oe(false);
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let mut data: u8 = 0;
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// MSB first
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for bit in (0..8).rev() {
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self.unit_delay();
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self.scl_oe(false);
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self.unit_delay();
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if self.sda_i() { data |= 1 << bit }
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self.scl_oe(true);
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}
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// Send ack/nack (true = nack, false = ack)
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self.sda_oe(ack);
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self.unit_delay();
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self.scl_oe(false);
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self.unit_delay();
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self.scl_oe(true);
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self.sda_oe(true);
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// postcondition: SCL and SDA low
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Ok(data)
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}
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pub fn pca954x_select(&mut self, address: u8, channel: Option<u8>) -> Result<(), &'static str> {
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self.start()?;
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// PCA9547 supports only one channel at a time
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// for compatibility, PCA9548 is treated as such too
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// channel - Some(x) - # of the channel [0,7], or None for all disabled
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let setting = match self.pca_type {
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I2cMultiplexer::PCA9548 => {
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match channel {
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Some(ch) => 1 << ch,
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None => 0,
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}
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},
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#[cfg(feature = "target_kasli_soc")]
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I2cMultiplexer::PCA9547 => {
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match channel {
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Some(ch) => ch | 0x08,
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None => 0,
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}
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}
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};
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if !self.write(address << 1)? {
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return Err("PCA954X failed to ack write address")
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}
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if !self.write(setting)? {
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return Err("PCA954X failed to ack control word")
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}
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self.stop()?;
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Ok(())
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}
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}
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