szl: change CPU frequency of Kasli-SoC to 1 GHz #99

Merged
sb10q merged 1 commits from occheung/zynq-rs:fix_clk_freq into master 2022-07-20 16:55:17 +08:00

Test

Built both gateware & firmware of a small system, loaded in a Kasli-SoC.
artiq_sinara_tester blinked the LED.

The following test code was inserted into the main_core0() function in artiq-zynq runtime after "NAR3/Zynq7000 starting..." was logged.

    let clk_frequency = Clocks::get().cpu_6x4x();
    info!("cpu_6x4x: {}", clk_frequency);

Clocks was imported from libboard_zynq::clocks::Clocks in prior.
It produced this trace in serial logging.

[     0.000067s]  INFO(runtime): NAR3/Zynq7000 starting...
[     0.005235s]  INFO(runtime): cpu_6x4x: 999999990

It was 799999992 before this patch.

## Test Built both gateware & firmware of a small system, loaded in a Kasli-SoC. `artiq_sinara_tester` blinked the LED. The following test code was inserted into the `main_core0()` function in artiq-zynq runtime after "NAR3/Zynq7000 starting..." was logged. ```rust let clk_frequency = Clocks::get().cpu_6x4x(); info!("cpu_6x4x: {}", clk_frequency); ``` `Clocks` was imported from `libboard_zynq::clocks::Clocks` in prior. It produced this trace in serial logging. ``` [ 0.000067s] INFO(runtime): NAR3/Zynq7000 starting... [ 0.005235s] INFO(runtime): cpu_6x4x: 999999990 ``` It was `799999992` before this patch.
occheung added 1 commit 2022-07-20 16:52:33 +08:00
sb10q merged commit 043a152b91 into master 2022-07-20 16:55:17 +08:00
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Reference: M-Labs/zynq-rs#99
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