libcortex_a9: added interrupt_handler macro #77

Merged
sb10q merged 1 commits from pca006132/zynq-rs:master into master 2024-08-17 17:37:18 +08:00
5 changed files with 39 additions and 11 deletions

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@ -34,6 +34,20 @@ SECTIONS
__bss_end = .; __bss_end = .;
} > OCM3 } > OCM3
.irq_stack1 (NOLOAD) : ALIGN(8)
{
__irq_stack1_end = .;
. += 0x100;
__irq_stack1_start = .;
} > OCM3
.irq_stack0 (NOLOAD) : ALIGN(8)
{
__irq_stack0_end = .;
. += 0x100;
__irq_stack0_start = .;
} > OCM3
.stack1 (NOLOAD) : ALIGN(8) { .stack1 (NOLOAD) : ALIGN(8) {
__stack1_end = .; __stack1_end = .;
. += 0x200; . += 0x200;

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@ -55,7 +55,7 @@ extern "C" {
static CORE1_RESTART: AtomicBool = AtomicBool::new(false); static CORE1_RESTART: AtomicBool = AtomicBool::new(false);
interrupt_handler!(IRQ, irq, __stack0_start, __stack1_start, { interrupt_handler!(IRQ, irq, __irq_stack0_start, __irq_stack1_start, {
Outdated
Review

Still the main stack?

Still the main stack?

sorry I forgot this one, fixed.

sorry I forgot this one, fixed.
if MPIDR.read().cpu_id() == 1{ if MPIDR.read().cpu_id() == 1{
let mpcore = mpcore::RegisterBlock::mpcore(); let mpcore = mpcore::RegisterBlock::mpcore();
let mut gic = gic::InterruptController::gic(mpcore); let mut gic = gic::InterruptController::gic(mpcore);

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@ -2,25 +2,25 @@ use libregister::RegisterR;
use libcortex_a9::{regs::{DFSR, MPIDR}, interrupt_handler}; use libcortex_a9::{regs::{DFSR, MPIDR}, interrupt_handler};
use libboard_zynq::{println, stdio}; use libboard_zynq::{println, stdio};
interrupt_handler!(UndefinedInstruction, undefined_instruction, __stack0_start, __stack1_start, { interrupt_handler!(UndefinedInstruction, undefined_instruction, __irq_stack0_start, __irq_stack1_start, {
Outdated
Review

I think we probably want to inspect the main stack when this happens... so it should not get mangled.

I think we probably want to inspect the main stack when this happens... so it should not get mangled.
stdio::drop_uart(); stdio::drop_uart();
println!("UndefinedInstruction"); println!("UndefinedInstruction");
loop {} loop {}
}); });
interrupt_handler!(SoftwareInterrupt, software_interrupt, __stack0_start, __stack1_start, { interrupt_handler!(SoftwareInterrupt, software_interrupt, __irq_stack0_start, __irq_stack1_start, {
stdio::drop_uart(); stdio::drop_uart();
println!("SoftwareInterrupt"); println!("SoftwareInterrupt");
loop {} loop {}
}); });
interrupt_handler!(PrefetchAbort, prefetch_abort, __stack0_start, __stack1_start, { interrupt_handler!(PrefetchAbort, prefetch_abort, __irq_stack0_start, __irq_stack1_start, {
stdio::drop_uart(); stdio::drop_uart();
println!("PrefetchAbort"); println!("PrefetchAbort");
loop {} loop {}
}); });
interrupt_handler!(DataAbort, data_abort, __stack0_start, __stack1_start, { interrupt_handler!(DataAbort, data_abort, __irq_stack0_start, __irq_stack1_start, {
stdio::drop_uart(); stdio::drop_uart();
println!("DataAbort on core {}", MPIDR.read().cpu_id()); println!("DataAbort on core {}", MPIDR.read().cpu_id());
@ -29,20 +29,20 @@ interrupt_handler!(DataAbort, data_abort, __stack0_start, __stack1_start, {
loop {} loop {}
}); });
interrupt_handler!(ReservedException, reserved_exception, __stack0_start, __stack1_start, { interrupt_handler!(ReservedException, reserved_exception, __irq_stack0_start, __irq_stack1_start, {
stdio::drop_uart(); stdio::drop_uart();
println!("ReservedException"); println!("ReservedException");
loop {} loop {}
}); });
#[cfg(feature = "dummy_irq_handler")] #[cfg(feature = "dummy_irq_handler")]
interrupt_handler!(IRQ, irq, __stack0_start, __stack1_start, { interrupt_handler!(IRQ, irq, __irq_stack0_start, __irq_stack1_start, {
stdio::drop_uart(); stdio::drop_uart();
println!("IRQ"); println!("IRQ");
loop {} loop {}
}); });
interrupt_handler!(FIQ, fiq, __stack0_start, __stack1_start, { interrupt_handler!(FIQ, fiq, __irq_stack0_start, __irq_stack1_start, {
stdio::drop_uart(); stdio::drop_uart();
println!("FIQ"); println!("FIQ");
loop {} loop {}

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@ -2,7 +2,7 @@ use r0::zero_bss;
use core::ptr::write_volatile; use core::ptr::write_volatile;
use libregister::{ use libregister::{
VolatileCell, VolatileCell,
RegisterR, RegisterW, RegisterRW, RegisterR, RegisterRW,
}; };
use libcortex_a9::{asm, l2c, regs::*, cache, mmu, spin_lock_yield, notify_spin_lock, enable_fpu, interrupt_handler}; use libcortex_a9::{asm, l2c, regs::*, cache, mmu, spin_lock_yield, notify_spin_lock, enable_fpu, interrupt_handler};
use libboard_zynq::{slcr, mpcore}; use libboard_zynq::{slcr, mpcore};
@ -19,16 +19,15 @@ extern "C" {
static mut CORE1_ENABLED: VolatileCell<bool> = VolatileCell::new(false); static mut CORE1_ENABLED: VolatileCell<bool> = VolatileCell::new(false);
interrupt_handler!(Reset, reset_irq, __stack0_start, __stack1_start, { interrupt_handler!(Reset, reset_irq, __stack0_start, __stack1_start, {
// no need to setup stack here, as we already did when entering the handler
match MPIDR.read().cpu_id() { match MPIDR.read().cpu_id() {
0 => { 0 => {
SP.write(&mut __stack0_start as *mut _ as u32);
boot_core0(); boot_core0();
} }
1 => { 1 => {
while !CORE1_ENABLED.get() { while !CORE1_ENABLED.get() {
spin_lock_yield(); spin_lock_yield();
} }
SP.write(&mut __stack1_start as *mut _ as u32);
boot_core1(); boot_core1();
} }
_ => unreachable!(), _ => unreachable!(),

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@ -59,6 +59,21 @@ SECTIONS
__stack0_start = .; __stack0_start = .;
} > OCM3 } > OCM3
.irq_stack1 (NOLOAD) : ALIGN(8)
{
__irq_stack1_end = .;
. += 0x100;
__irq_stack1_start = .;
} > OCM3
.irq_stack0 (NOLOAD) : ALIGN(8)
{
__irq_stack0_end = .;
. += 0x100;
__irq_stack0_start = .;
} > OCM3
/DISCARD/ : /DISCARD/ :
{ {
/* Unused exception related info that only wastes space */ /* Unused exception related info that only wastes space */