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l2c related changes #76

Merged
sb10q merged 2 commits from pca006132/zynq-rs:master into master 2021-01-26 12:01:24 +08:00
Conversation 1 Commits 2 Files Changed 3
3 changed files with 7 additions and 4 deletions
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7
libcortex_a9/src/l2c.rs
View File

@ -2,7 +2,9 @@ use libregister::{register, register_at, register_bit, register_bits, RegisterRW
use super::asm::dmb;
use volatile_register::RW;
pub fn enable_l2_cache() {
/// enable L2 cache with specific prefetch offset
/// prefetch offset requires manual tuning, it seems that 8 is good for ZC706 current settings
pub fn enable_l2_cache(offset: u8) {
dmb();
let regs = RegisterBlock::new();
// disable L2 cache
@ -14,6 +16,7 @@ pub fn enable_l2_cache() {
.double_linefill_en(true)
.incr_double_linefill_en(true)
.pref_drop_en(true)
.prefetch_offset(offset)
);
regs.reg1_aux_control.modify(|_, w| {
w.early_bresp_en(true)
@ -326,3 +329,5 @@ register_bit!(reg15_prefetch_ctrl, instr_prefetch_en, 29);
register_bit!(reg15_prefetch_ctrl, data_prefetch_en, 28);
register_bit!(reg15_prefetch_ctrl, pref_drop_en, 24);
register_bit!(reg15_prefetch_ctrl, incr_double_linefill_en, 23);
register_bits!(reg15_prefetch_ctrl, prefetch_offset, u8, 0, 4);

2
libcortex_a9/src/regs.rs
View File

@ -173,7 +173,7 @@ impl RegisterRW for ACTLR {
impl ACTLR {
pub fn enable_smp(&mut self) {
self.modify(|_, w| w.smp(true).fw(true));
self.modify(|_, w| w.smp(true).fw(true).alloc_one_way(true));
}
pub fn enable_prefetch(&mut self) {

2
szl/src/main.rs
View File

@ -20,7 +20,6 @@ use libconfig::{bootgen, sd_reader, Config};
use libcortex_a9::{
asm::{dsb, isb},
cache::{bpiall, dcciall, iciallu},
l2c::enable_l2_cache,
};
use libregister::RegisterR;
use libsupport_zynq::ram;
@ -80,7 +79,6 @@ pub fn main_core0() {
"#
);
info!("Simple Zynq Loader starting...");
enable_l2_cache();
const CPU_FREQ: u32 = 800_000_000;