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l2c related changes #76

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sb10q merged 1 commits from pca006132/zynq-rs:master into master 2024-08-17 17:37:18 +08:00
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pca006132 commented 2021-01-26 11:22:54 +08:00
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  1. Enabled some options to optimize memcpy throughput. Tests on zeus shows minor improvement in RPC throughput.
  2. Removed L2C enable code from SZL, move to artiq-zynq to stay compatible with FSBL.

Note: Some CPU options for performance optimizations are still missing from FSBL.

1. Enabled some options to optimize `memcpy` throughput. Tests on zeus shows minor improvement in RPC throughput. 2. Removed L2C enable code from SZL, move to artiq-zynq to stay compatible with FSBL. Note: Some CPU options for performance optimizations are still missing from FSBL.
pca006132 added 2 commits 2021-01-26 11:22:54 +08:00
pca006132 commented 2021-01-26 11:24:27 +08:00
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Reference:

By default, the prefetch offset is 5'b00000. For example, if S0 receives a cacheable read at address 0x100, the cache line at address 0x120 is prefetched. Prefetching the following cache line might not result in optimal performance. In some systems, it might be better to prefetch more in advance to achieve better performance. The prefetch offset enables this by setting the address of the prefetched cache line to Cache Line + 1 + Offset. The optimal value of the prefetch offset depends on the L3 read latency and on the L1 read issuing capability. It is recommended to perform system experiments by varying the prefetch offset, to find the optimal value.

https://developer.arm.com/documentation/ddi0246/d/functional-overview/implementation-details/prefetching-operation

Reference: > By default, the prefetch offset is 5'b00000. For example, if S0 receives a cacheable read at address 0x100, the cache line at address 0x120 is prefetched. Prefetching the following cache line might not result in optimal performance. In some systems, it might be better to prefetch more in advance to achieve better performance. The prefetch offset enables this by setting the address of the prefetched cache line to Cache Line + 1 + Offset. The optimal value of the prefetch offset depends on the L3 read latency and on the L1 read issuing capability. It is recommended to perform system experiments by varying the prefetch offset, to find the optimal value. https://developer.arm.com/documentation/ddi0246/d/functional-overview/implementation-details/prefetching-operation
sb10q merged commit 6e6612bc3e into master 2021-01-26 12:01:24 +08:00
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Reference: M-Labs/zynq-rs#76
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