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L2 cache #64

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sb10q merged 1 commits from pca006132/zynq-rs:l2-cache into master 2020-08-20 17:18:36 +08:00
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pca006132 commented 2020-08-20 12:06:42 +08:00
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Enabled L2 cache

Enabled L2 cache
sb10q commented 2020-08-20 12:13:17 +08:00
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What is the testing level with artiq-zynq (including DMA and analyzer) and impact on performance?

What is the testing level with artiq-zynq (including DMA and analyzer) and impact on performance?
pca006132 commented 2020-08-20 12:32:49 +08:00
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I haven't done any benchmarks. I've tested it with the test scripts in https://github.com/m-labs/artiq/tree/master/artiq/test/coredevice, and nothing breaks. I've refactored the L2C code a bit but in theory nothing should break.

For performance, I've only tested it with ACPKI, and it could reduce the sustained output rate from 490ns to 390ns.

There are other performance problems in both the firmware and python side, which I would resolve them later. Cache is not our bottleneck, so the performance difference is not huge.

Edit: test_performance.py indicates that our speed for copying is increased by about 30%... That is a bug in the test_performance.py as it should be testing the network throughput instead of CPU memory copy throughput, but that could serve as a microbenchmark though...

I haven't done any benchmarks. I've tested it with the test scripts in https://github.com/m-labs/artiq/tree/master/artiq/test/coredevice, and nothing breaks. I've refactored the L2C code a bit but in theory nothing should break. For performance, I've only tested it with ACPKI, and it could reduce the sustained output rate from 490ns to 390ns. There are other performance problems in both the firmware and python side, which I would resolve them later. Cache is not our bottleneck, so the performance difference is not huge. Edit: `test_performance.py` indicates that our speed for copying is increased by about 30%... That is a bug in the `test_performance.py` as it should be testing the network throughput instead of CPU memory copy throughput, but that could serve as a microbenchmark though...
sb10q reviewed 2020-08-20 12:36:17 +08:00
experiments/src/main.rs Outdated
@ -86,6 +87,7 @@ pub fn restart_core1() {
#[no_mangle]
pub fn main_core0() {
// zynq::clocks::CpuClocks::enable_io(1_250_000_000);
start_l2_cache();
sb10q commented 2020-08-20 12:36:17 +08:00
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Nitpick: this is usually called "enable" or "init" elsewhere in the code and not "start".

Nitpick: this is usually called "enable" or "init" elsewhere in the code and not "start".
sb10q closed this pull request 2020-08-20 17:18:36 +08:00
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Reference: M-Labs/zynq-rs#64
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