DDR: fixed register write. #44

Merged

sb10q merged 1 commits from pca006132/zynq-rs:master into master

2020-07-06 11:46:38 +08:00

Author	SHA1	Message	Date
pca006132	29b8615e45	DDR: fixed register write. Previously it writes `0x20066`, while the ps7_init set it to be `0x200066`, notice the 1 more 0. This should perform the same writes to the registers, so we do not have to apply the ps7_init in artiq_zynq.	2020-07-06 11:40:21 +08:00

Author

SHA1

Message

Date

pca006132

29b8615e45

DDR: fixed register write.

Previously it writes `0x20066`, while the ps7_init set it to be
`0x200066`, notice the 1 more 0.
This should perform the same writes to the registers, so we do not have
to apply the ps7_init in artiq_zynq.

2020-07-06 11:40:21 +08:00

DDR: fixed register write. #44

1 Commits (master)