libboard_zynq/src/sdio/regs.rs

@@ -20,6 +20,41 @@ pub enum ResponseTypeSelect {
     Legnth48Check = 0b11,
 }
 
+#[allow(unused)]
+#[repr(u8)]
+pub enum BusVoltage {
+    /// 3.3V
+    v33 = 0b111,
+    /// 3.0V, typ.
+    v30 = 0b110,
+    /// 1.8V, typ.
+    v18 = 0b101,
+}
+
+#[allow(unused)]
+#[repr(u8)]
+pub enum DmaSelect {
+    sdma = 0b00,
+    adma1 = 0b01,
+    adma2 = 0b10,
+    adma3 = 0b11,
+}
+
+#[allow(unused)]
+#[repr(u8)]
+/// SDCLK Frequency divisor, d(number) means baseclock divides by (number).
+pub enum SdclkFreqDivisor {
+    d256 = 0x80,
+    d128 = 0x40,
+    d64 = 0x20,
+    d32 = 0x10,
+    d16 = 0x08,
+    d8 = 0x04,
+    d4 = 0x02,
+    d2 = 0x01,
+    d1 = 0x00,
+}
+
 #[repr(C)]
 pub struct RegisterBlock {
     pub sdma_system_address: RM<u32>,
@@ -29,6 +64,10 @@ pub struct RegisterBlock {
     pub responses: [RO<u32>; 4],
     pub buffer: RW<u32>,
     pub present_state: PresentState,
+    /// Host. power, block gap, wakeup control
+    pub control: Control,
+    /// Clock and timeout control, and software reset register.
+    pub timing_control: TimingControl,
 }
 
 register_at!(RegisterBlock, 0xE0100000, sd0);
@@ -60,7 +99,6 @@ register_bits!(
     11
 );
 
-
 register!(transfer_mode_command, TransferModeCommand, RW, u32);
 register_bits!(
     transfer_mode_command,
@@ -137,7 +175,6 @@ register_bit!(
     0
 );
 
-
 register!(present_state, PresentState, RO, u32);
 register_bit!(
     present_state,
@@ -181,48 +218,131 @@ register_bit!(
     card_detected,
     18
 );
-regsiter_bit!(
+regsiter_bit!(present_state, card_state_stable, 17);
-    present_state,
+register_bit!(present_state, card_inserted, 16);
-    card_state_stable,
+register_bit!(present_state, buffer_read_en, 11,);
+register_bit!(present_state, buffer_write_en, 10);
+register_bit!(present_state, read_transfer_active, 9);
+register_bit!(present_state, write_transfer_active, 8);
+register_bit!(present_state, dat_line_active, 2);
+register_bit!(present_state, command_inhibit_dat, 1);
+register_bit!(present_state, command_inhibit_cmd, 0);
+
+register!(control, Control, RW, u32);
+register_bit!(
+    contorl,
+    /// Enable wakeup event via SD card removal assertion.
+    wakeup_on_removal,
+    26
+);
+register_bit!(
+    control,
+    /// Enable wakeup event via SD card insertion assertion.
+    wakeup_on_insertion,
+    25
+);
+register_bit!(
+    control,
+    /// Enable wakeup event via card interrupt assertion.
+    wakeup_on_interrupt,
+    24
+);
+register_bit!(
+    control,
+    ///Enable interrupt detection at the block gap for a multiple block transfer.
+    interrupt_at_block_gap,
+    19
+);
+register_bit!(
+    control,
+    /// Enable the use of the read wait protocol.
+    read_wait_control,
+    18
+);
+register_bit!(
+    control,
+    /// Restart a trasaction which was stopped using the stop at block gap request.
+    continue_req,
     17
 );
 register_bit!(
-    present_state,
+    control,
-    card_inserted,
+    /// Stop executing a transaction at the next block gap.
+    stop_at_block_gap_req,
     16
 );
+register_bits_typed!(control, bus_voltage, u8, BusVoltage, 9, 11);
+register_bit!(control, bus_power, 8);
 register_bit!(
-    present_state,
+    control,
-    buffer_read_en,
+    /// Selects source for card detection. 0 for SDCD#, 1 for card detect test level.
-    11,
+    card_detect_signal,
+    7
 );
 register_bit!(
-    present_state,
+    control,
-    buffer_write_en,
+    /// Indicates card inserted or not. Enabled when card detect signal is 1.
-    10
+    card_detect_test_level,
+    6
 );
+register_bits_typed!(control, dma_select, u8, DmaSelect, 3, 4);
+register_bit!(control, high_speed_en, 2);
 register_bit!(
-    present_state,
+    control,
-    read_transfer_active,
+    /// Select the data width of the HC. 1 for 4-bit, 0 for 1-bit.
-    9
+    data_width_select,
-);
-register_bit!(
-    present_state,
-    write_transfer_active,
-    8
-);
-register_bit!(
-    present_state,
-    dat_line_active,
-    2
-);
-register_bit!(
-    present_state,
-    command_inhibit_dat,
     1
 );
 register_bit!(
-    present_state,
+    control,
-    command_inhibit_cmd,
+    /// 1 for LED on, 0 for LED off.
+    led_control,
     0
-);
+);
+
+register!(timing_control, TimingControl, RW, u32);
+register_bit!(
+    timing_control,
+    /// Software reset for DAT line.
+    software_reset_dat,
+    26
+);
+register_bit!(
+    timing_control,
+    /// Software reset for CMD line.
+    software_reset_cmd,
+    25
+);
+register_bit!(
+    timing_control,
+    /// Software reset for ALL.
+    software_reset_all,
+    24
+);
+register_bits!(
+    timing_control,
+    /// Determines the interval by which DAT line time-outs are detected.
+    /// Interval = TMCLK * 2^(13 + val)
+    /// Note: 0b1111 is reserved.
+    timeout_counter_value,
+    u8,
+    16,
+    19
+);
+register_bits_typed!(
+    timing_control,
+    /// Selects the frequency divisor, thus the clock frequency for SDCLK.
+    /// Choose the smallest possible divisor which results in a clock frequency
+    /// that is less than or equal to the target frequency.
+    sdclk_freq_divisor,
+    u8,
+    SdclkFreqDivisor,
+    8,
+    15
+);
+register_bits!(timing_control, sd_clk_en, 2);
+register_bits!(timing_control,
+    /// 1 when SD clock is stable.
+    /// Note that this field is read-only.
+    internal_clk_stable, 1);
+register_bits!(timing_control, internal_clk_en, 0);