kasli-soc: Ethernet PHY not detected #78

New Issue

sb10q · 2021-05-28T18:20:21+08:00

sb10q commented

2021-05-28 18:20:21 +08:00

identify_phy() always returns None in Phy.find().

``identify_phy()`` always returns ``None`` in ``Phy.find()``.

sb10q commented

2021-05-28 19:18:12 +08:00

Poster

Only MDIO seems broken, board responds to ping after hardcoding PHY autodetection and link status.

diff --git a/libboard_zynq/src/eth/mod.rs b/libboard_zynq/src/eth/mod.rs
index e8e56e4..a4eb143 100644
--- a/libboard_zynq/src/eth/mod.rs
+++ b/libboard_zynq/src/eth/mod.rs
@@ -308,8 +308,8 @@ impl<GEM: Gem> Eth<GEM, (), ()> {
         inner.configure(macaddr);
 
         let phy = Phy::find(&mut inner).expect("phy");
-        phy.reset(&mut inner);
-        phy.restart_autoneg(&mut inner);
+        //phy.reset(&mut inner);
+        //phy.restart_autoneg(&mut inner);
 
         Eth {
             rx: (),
diff --git a/libboard_zynq/src/eth/phy/mod.rs b/libboard_zynq/src/eth/phy/mod.rs
index 9fdfbc7..fa65dcf 100644
--- a/libboard_zynq/src/eth/phy/mod.rs
+++ b/libboard_zynq/src/eth/phy/mod.rs
@@ -43,7 +43,7 @@ const OUI_LANTIQ : u32 = 0x355969;
 impl Phy {
     /// Probe all addresses on MDIO for a known PHY
     pub fn find<PA: PhyAccess>(pa: &mut PA) -> Option<Phy> {
-        (1..32).find(|addr| {
+        /*(1..32).find(|addr| {
             match identify_phy(pa, *addr) {
                 Some(PhyIdentifier {
                     oui: OUI_MARVELL,
@@ -71,7 +71,8 @@ impl Phy {
                 }) => true,
                 _ => false,
             }
-        }).map(|addr| Phy { addr })
+        }).map(|addr| Phy { addr })*/
+        Some(Phy { addr: 5 })
     }
 
     pub fn read_reg<PA, PR>(&self, pa: &mut PA) -> PR
@@ -110,15 +111,10 @@ impl Phy {
     }
 
     pub fn get_link<PA: PhyAccess>(&self, pa: &mut PA) -> Option<Link> {
-        let status = self.get_status(pa);
-        if !status.link_status() {
-            None
-        } else if status.cap_1000base_t_extended_status() {
-            let phy_status: PSSR = self.read_reg(pa);
-            phy_status.get_link()
-        } else {
-            status.get_link()
-        }
+        Some(Link {
+            speed: LinkSpeed::S1000,
+            duplex: LinkDuplex::Full,
+        })
     }
 
     pub fn reset<PA: PhyAccess>(&self, pa: &mut PA) {

Only MDIO seems broken, board responds to ping after hardcoding PHY autodetection and link status. ``` diff --git a/libboard_zynq/src/eth/mod.rs b/libboard_zynq/src/eth/mod.rs index e8e56e4..a4eb143 100644 --- a/libboard_zynq/src/eth/mod.rs +++ b/libboard_zynq/src/eth/mod.rs @@ -308,8 +308,8 @@ impl<GEM: Gem> Eth<GEM, (), ()> { inner.configure(macaddr); let phy = Phy::find(&mut inner).expect("phy"); - phy.reset(&mut inner); - phy.restart_autoneg(&mut inner); + //phy.reset(&mut inner); + //phy.restart_autoneg(&mut inner); Eth { rx: (), diff --git a/libboard_zynq/src/eth/phy/mod.rs b/libboard_zynq/src/eth/phy/mod.rs index 9fdfbc7..fa65dcf 100644 --- a/libboard_zynq/src/eth/phy/mod.rs +++ b/libboard_zynq/src/eth/phy/mod.rs @@ -43,7 +43,7 @@ const OUI_LANTIQ : u32 = 0x355969; impl Phy { /// Probe all addresses on MDIO for a known PHY pub fn find<PA: PhyAccess>(pa: &mut PA) -> Option<Phy> { - (1..32).find(|addr| { + /*(1..32).find(|addr| { match identify_phy(pa, *addr) { Some(PhyIdentifier { oui: OUI_MARVELL, @@ -71,7 +71,8 @@ impl Phy { }) => true, _ => false, } - }).map(|addr| Phy { addr }) + }).map(|addr| Phy { addr })*/ + Some(Phy { addr: 5 }) } pub fn read_reg<PA, PR>(&self, pa: &mut PA) -> PR @@ -110,15 +111,10 @@ impl Phy { } pub fn get_link<PA: PhyAccess>(&self, pa: &mut PA) -> Option<Link> { - let status = self.get_status(pa); - if !status.link_status() { - None - } else if status.cap_1000base_t_extended_status() { - let phy_status: PSSR = self.read_reg(pa); - phy_status.get_link() - } else { - status.get_link() - } + Some(Link { + speed: LinkSpeed::S1000, + duplex: LinkDuplex::Full, + }) } pub fn reset<PA: PhyAccess>(&self, pa: &mut PA) { ```

sb10q commented

2021-05-29 07:15:02 +08:00

Poster

Might be the cause: https://github.com/sinara-hw/Kasli-SOC/issues/53

sb10q commented

2021-05-29 10:52:48 +08:00

Poster

Resetting the PHY in the firmware does not help. I am sure that this code works because executing it causes the Ethernet link to drop on the switch during the PHY reset.

reset_phy_hack.diff

3.2 KiB

sb10q referenced this issue from a commit

2021-05-29 12:50:43 +08:00

libboard_zynq: work around Kasli-SoC MDIO breakage (#78)

sb10q commented

2021-07-05 13:39:07 +08:00

Poster

a42e5a95ff

https://git.m-labs.hk/M-Labs/zynq-rs/commit/a42e5a95ffa77912dcac54ceb5a8b65ca7ce92ba

sb10q closed this issue

2021-07-05 13:39:07 +08:00