support pynqz2

libboard_zynq/Cargo.toml

@@ -11,6 +11,7 @@ target_coraz7 = []
 target_ebaz4205 = []
 target_redpitaya = []
 target_kasli_soc = []
+target_pynqz2 = []
 ipv6 = [ "smoltcp/proto-ipv6" ]
 
 [dependencies]

libboard_zynq/src/clocks/source.rs

@@ -12,6 +12,8 @@ pub const PS_CLK: u32 = 33_333_333;
 pub const PS_CLK: u32 = 33_333_333;
 #[cfg(feature = "target_kasli_soc")]
 pub const PS_CLK: u32 = 33_333_333;
+#[cfg(feature = "target_pynqz2")]
+pub const PS_CLK: u32 = 50_000_000;
 
 /// (pll_fdiv_max, (pll_cp, pll_res, lock_cnt))
 const PLL_FDIV_LOCK_PARAM: &[(u16, (u8, u8, u16))] = &[

libcortex_a9/src/uncached.rs

@@ -19,8 +19,8 @@ impl<T> UncachedSlice<T> {
             .max(L1_PAGE_SIZE);
         let layout = Layout::from_size_align(size, align)?;
         let ptr = unsafe { alloc::alloc::alloc(layout).cast::<T>() };
-        assert!(!ptr.is_null());
         let start = ptr as usize;
+        assert_eq!(start & (L1_PAGE_SIZE - 1), 0);
 
         for page_start in (start..(start + size)).step_by(L1_PAGE_SIZE) {
             // non-shareable device
@@ -33,6 +33,9 @@ impl<T> UncachedSlice<T> {
         }
 
         let slice = unsafe { core::slice::from_raw_parts_mut(ptr, len) };
+        // verify size
+        assert!(unsafe { slice.get_unchecked(len) } as *const _ as usize <= start + size);
+        // initialize
         for e in slice.iter_mut() {
             *e = default();
         }