main: refactor into boot

src/abort.rs

@@ -0,0 +1,13 @@
+use crate::println;
+
+#[no_mangle]
+pub unsafe extern "C" fn PrefetchAbort() {
+    println!("PrefetchAbort");
+    loop {}
+}
+
+#[no_mangle]
+pub unsafe extern "C" fn DataAbort() {
+    println!("DataAbort");
+    loop {}
+}

src/boot.rs

@@ -0,0 +1,61 @@
+use r0::zero_bss;
+use crate::regs::{RegisterR, RegisterW};
+use crate::cortex_a9::{asm, regs::*, mmu};
+
+extern "C" {
+    static mut __bss_start: u32;
+    static mut __bss_end: u32;
+    static mut __stack_start: u32;
+}
+
+#[link_section = ".text.boot"]
+#[no_mangle]
+#[naked]
+pub unsafe extern "C" fn _boot_cores() -> ! {
+    const CORE_MASK: u32 = 0x3;
+
+    match MPIDR.read() & CORE_MASK {
+        0 => {
+            SP.write(&mut __stack_start as *mut _ as u32);
+            boot_core0();
+        }
+        _ => loop {
+            // if not core0, infinitely wait for events
+            asm::wfe();
+        },
+    }
+}
+
+#[naked]
+#[inline(never)]
+unsafe fn boot_core0() -> ! {
+    l1_cache_init();
+    zero_bss(&mut __bss_start, &mut __bss_end);
+
+    let mmu_table = mmu::L1Table::get()
+        .setup_flat_layout();
+    mmu::with_mmu(mmu_table, || {
+        crate::main();
+        panic!("return from main");
+    });
+}
+
+fn l1_cache_init() {
+    use crate::cortex_a9::cache::*;
+
+    // Invalidate TLBs
+    tlbiall();
+    // Invalidate I-Cache
+    iciallu();
+    // Invalidate Branch Predictor Array
+    bpiall();
+    // Invalidate D-Cache
+    //
+    // NOTE: It is both faster and correct to only invalidate instead
+    //       of also flush the cache (as was done before with
+    //       `dccisw()`) and it is correct to perform this operation
+    //       for all of the L1 data cache rather than a (previously
+    //       unspecified) combination of one cache set and one cache
+    //       way.
+    dciall();
+}

src/main.rs

@@ -10,98 +10,32 @@
 #![allow(dead_code)]
 
 extern crate alloc;
-use alloc::{vec, vec::Vec, alloc::Layout};
+use alloc::{vec, vec::Vec};
-use core::alloc::GlobalAlloc;
+use core::mem::transmute;
-use core::ptr::NonNull;
-use core::cell::RefCell;
-use core::mem::{uninitialized, transmute};
-use r0::zero_bss;
 use compiler_builtins as _;
 use smoltcp::wire::{EthernetAddress, IpAddress, IpCidr};
-use smoltcp::iface::{NeighborCache, EthernetInterfaceBuilder, EthernetInterface};
+use smoltcp::iface::{NeighborCache, EthernetInterfaceBuilder};
 use smoltcp::time::Instant;
 use smoltcp::socket::SocketSet;
-use linked_list_allocator::Heap;
 
+mod boot;
 mod regs;
 mod cortex_a9;
-mod stdio;
+mod abort;
+mod panic;
 mod zynq;
-
+mod stdio;
-use crate::regs::{RegisterR, RegisterW};
+mod ram;
-use crate::cortex_a9::{asm, regs::*, mmu};
-
-extern "C" {
-    static mut __bss_start: u32;
-    static mut __bss_end: u32;
-    static mut __stack_start: u32;
-}
-
-#[link_section = ".text.boot"]
-#[no_mangle]
-#[naked]
-pub unsafe extern "C" fn _boot_cores() -> ! {
-    const CORE_MASK: u32 = 0x3;
-
-    match MPIDR.read() & CORE_MASK {
-        0 => {
-            SP.write(&mut __stack_start as *mut _ as u32);
-            boot_core0();
-        }
-        _ => loop {
-            // if not core0, infinitely wait for events
-            asm::wfe();
-        },
-    }
-}
-
-#[naked]
-#[inline(never)]
-unsafe fn boot_core0() -> ! {
-    l1_cache_init();
-    zero_bss(&mut __bss_start, &mut __bss_end);
-
-    let mmu_table = mmu::L1Table::get()
-        .setup_flat_layout();
-    mmu::with_mmu(mmu_table, || {
-        main();
-        panic!("return from main");
-    });
-}
-
-fn l1_cache_init() {
-    use crate::cortex_a9::cache::*;
-
-    // Invalidate TLBs
-    tlbiall();
-    // Invalidate I-Cache
-    iciallu();
-    // Invalidate Branch Predictor Array
-    bpiall();
-    // Invalidate D-Cache
-    //
-    // NOTE: It is both faster and correct to only invalidate instead
-    //       of also flush the cache (as was done before with
-    //       `dccisw()`) and it is correct to perform this operation
-    //       for all of the L1 data cache rather than a (previously
-    //       unspecified) combination of one cache set and one cache
-    //       way.
-    dciall();
-}
 
 const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
 
-fn main() {
+pub fn main() {
     println!("Main.");
 
     let mut ddr = zynq::ddr::DdrRam::new();
     println!("DDR: {:?}", ddr.status());
     ddr.memtest();
-
+    ram::init_alloc(&mut ddr);
-    unsafe {
-        ALLOCATOR.0.borrow_mut()
-            .init(ddr.ptr::<u8>() as usize, ddr.size());
-    }
 
     let eth = zynq::eth::Eth::default(HWADDR.clone());
     println!("Eth on");
@@ -128,7 +62,7 @@ fn main() {
 
     let ethernet_addr = EthernetAddress(HWADDR);
     // IP stack
-    let local_addr = IpAddress::v4(10, 0, 0, 1);
+    let local_addr = IpAddress::v4(192, 168, 1, 28);
     let mut ip_addrs = [IpCidr::new(local_addr, 24)];
     let mut neighbor_storage = vec![None; 256];
     let neighbor_cache = NeighborCache::new(&mut neighbor_storage[..]);
@@ -146,7 +80,7 @@ fn main() {
     let mut time = 0u32;
     loop {
         time += 1;
-        let timestamp = Instant::from_millis(time.into());
+        let timestamp = Instant::from_millis(time);
 
         match iface.poll(&mut sockets, timestamp) {
             Ok(_) => {},
@@ -181,52 +115,6 @@ fn main() {
         //     None => println!("eth tx shortage"),
         // }
     }
+
 }
 
-#[panic_handler]
-fn panic(info: &core::panic::PanicInfo) -> ! {
-    println!("\nPanic: {}", info);
-
-    zynq::slcr::RegisterBlock::unlocked(|slcr| slcr.soft_reset());
-    loop {}
-}
-
-#[global_allocator]
-static ALLOCATOR: HeapAlloc = HeapAlloc(RefCell::new(Heap::empty()));
-
-/// LockedHeap doesn't locking properly
-struct HeapAlloc(RefCell<Heap>);
-
-/// FIXME: unsound; lock properly
-unsafe impl Sync for HeapAlloc {}
-
-unsafe impl GlobalAlloc for HeapAlloc {
-    unsafe fn alloc(&self, layout: Layout) -> *mut u8 {
-        self.0.borrow_mut()
-            .allocate_first_fit(layout)
-            .ok()
-            .map_or(0 as *mut u8, |allocation| allocation.as_ptr())
-    }
-
-    unsafe fn dealloc(&self, ptr: *mut u8, layout: Layout) {
-        self.0.borrow_mut()
-            .deallocate(NonNull::new_unchecked(ptr), layout)
-    }
-}
-
-#[alloc_error_handler]
-fn alloc_error(_: core::alloc::Layout) -> ! {
-    panic!("alloc_error")
-}
-
-#[no_mangle]
-pub unsafe extern "C" fn PrefetchAbort() {
-    println!("PrefetchAbort");
-    loop {}
-}
-
-#[no_mangle]
-pub unsafe extern "C" fn DataAbort() {
-    println!("DataAbort");
-    loop {}
-}

src/main.rs.orig

@@ -0,0 +1,185 @@
+#![no_std]
+#![no_main]
+#![feature(asm)]
+#![feature(global_asm)]
+#![feature(naked_functions)]
+#![feature(compiler_builtins_lib)]
+#![feature(never_type)]
+// TODO: disallow unused/dead_code when code moves into a lib crate
+#![allow(dead_code)]
+
+use core::mem::{uninitialized, transmute};
+use r0::zero_bss;
+use compiler_builtins as _;
+use smoltcp::wire::{EthernetAddress, IpAddress, IpCidr};
+use smoltcp::iface::{NeighborCache, EthernetInterfaceBuilder, EthernetInterface};
+use smoltcp::time::Instant;
+use smoltcp::socket::SocketSet;
+
+mod regs;
+mod cortex_a9;
+mod clocks;
+mod slcr;
+mod uart;
+mod stdio;
+mod eth;
+
+use crate::regs::{RegisterR, RegisterW};
+use crate::cortex_a9::{asm, regs::*, mmu};
+
+extern "C" {
+    static mut __bss_start: u32;
+    static mut __bss_end: u32;
+    static mut __stack_start: u32;
+}
+
+#[link_section = ".text.boot"]
+#[no_mangle]
+#[naked]
+pub unsafe extern "C" fn _boot_cores() -> ! {
+    const CORE_MASK: u32 = 0x3;
+
+    match MPIDR.read() & CORE_MASK {
+        0 => {
+            SP.write(&mut __stack_start as *mut _ as u32);
+            boot_core0();
+        }
+        _ => loop {
+            // if not core0, infinitely wait for events
+            asm::wfe();
+        },
+    }
+}
+
+#[naked]
+#[inline(never)]
+unsafe fn boot_core0() -> ! {
+    l1_cache_init();
+    zero_bss(&mut __bss_start, &mut __bss_end);
+
+    let mmu_table = mmu::L1Table::get()
+        .setup_flat_layout();
+    mmu::with_mmu(mmu_table, || {
+        main();
+        panic!("return from main");
+    });
+}
+
+fn l1_cache_init() {
+    // Invalidate TLBs
+    tlbiall();
+    // Invalidate I-Cache
+    iciallu();
+    // Invalidate Branch Predictor Array
+    bpiall();
+    // Invalidate D-Cache
+    dccisw();
+}
+
+const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
+
+fn main() {
+    println!("Main.");
+    let clocks = clocks::CpuClocks::get();
+    println!("Clocks: {:?}", clocks);
+    println!("CPU speeds: {}/{}/{}/{} MHz",
+             clocks.cpu_6x4x() / 1_000_000,
+             clocks.cpu_3x2x() / 1_000_000,
+             clocks.cpu_2x() / 1_000_000,
+             clocks.cpu_1x() / 1_000_000);
+
+    let eth = eth::Eth::default(HWADDR.clone());
+    println!("Eth on");
+
+    const RX_LEN: usize = 2;
+    let mut rx_descs: [eth::rx::DescEntry; RX_LEN] = unsafe { uninitialized() };
+    let mut rx_buffers = [[0u8; eth::MTU]; RX_LEN];
+    // Number of transmission buffers (minimum is two because with
+    // one, duplicate packet transmission occurs)
+    const TX_LEN: usize = 2;
+    let mut tx_descs: [eth::tx::DescEntry; TX_LEN] = unsafe { uninitialized() };
+    let mut tx_buffers = [[0u8; eth::MTU]; TX_LEN];
+    let eth = eth.start_rx(&mut rx_descs, &mut rx_buffers);
+    //let mut eth = eth.start_tx(&mut tx_descs, &mut tx_buffers);
+    let mut eth = eth.start_tx(
+        // HACK
+        unsafe { transmute(tx_descs.as_mut()) },
+        unsafe { transmute(tx_buffers.as_mut()) },
+    );
+
+    let ethernet_addr = EthernetAddress(HWADDR);
+    // IP stack
+    let local_addr = IpAddress::v4(10, 0, 0, 1);
+    let mut ip_addrs = [IpCidr::new(local_addr, 24)];
+    let mut neighbor_storage = [None; 16];
+    let neighbor_cache = NeighborCache::new(&mut neighbor_storage[..]);
+    let mut iface = EthernetInterfaceBuilder::new(&mut eth)
+        .ethernet_addr(ethernet_addr)
+        .ip_addrs(&mut ip_addrs[..])
+        .neighbor_cache(neighbor_cache)
+        .finalize();
+    let mut sockets_storage = [
+        None, None, None, None,
+        None, None, None, None
+    ];
+    let mut sockets = SocketSet::new(&mut sockets_storage[..]);
+
+    let mut time = 0u32;
+    loop {
+        time += 1;
+        let timestamp = Instant::from_millis(time.into());
+
+        match iface.poll(&mut sockets, timestamp) {
+            Ok(_) => {},
+            Err(e) => {
+                println!("poll error: {}", e);
+            }
+        }
+
+        // match eth.recv_next() {
+        //     Ok(Some(pkt)) => {
+        //         print!("eth: rx {} bytes", pkt.len());
+        //         for b in pkt.iter() {
+        //             print!(" {:02X}", b);
+        //         }
+        //         println!("");
+        //     }
+        //     Ok(None) => {}
+        //     Err(e) => {
+        //         println!("eth rx error: {:?}", e);
+        //     }
+        // }
+
+        // match eth.send(512) {
+        //     Some(mut pkt) => {
+        //         let mut x = 0;
+        //         for b in pkt.iter_mut() {
+        //             *b = x;
+        //             x += 1;
+        //         }
+        //         println!("eth tx {} bytes", pkt.len());
+        //     }
+        //     None => println!("eth tx shortage"),
+        // }
+    }
+}
+
+#[panic_handler]
+fn panic(info: &core::panic::PanicInfo) -> ! {
+    println!("\nPanic: {}", info);
+
+    slcr::RegisterBlock::unlocked(|slcr| slcr.soft_reset());
+    loop {}
+}
+
+#[no_mangle]
+pub unsafe extern "C" fn PrefetchAbort() {
+    println!("PrefetchAbort");
+    loop {}
+}
+
+#[no_mangle]
+pub unsafe extern "C" fn DataAbort() {
+    println!("DataAbort");
+    loop {}
+}

src/panic.rs

@@ -0,0 +1,9 @@
+use crate::{println, zynq};
+
+#[panic_handler]
+fn panic(info: &core::panic::PanicInfo) -> ! {
+    println!("\nPanic: {}", info);
+
+    zynq::slcr::RegisterBlock::unlocked(|slcr| slcr.soft_reset());
+    loop {}
+}

src/ram.rs

@@ -0,0 +1,42 @@
+use core::cell::RefCell;
+use core::alloc::GlobalAlloc;
+use core::ptr::NonNull;
+use alloc::alloc::Layout;
+use linked_list_allocator::Heap;
+use crate::zynq::ddr::DdrRam;
+
+#[global_allocator]
+static ALLOCATOR: HeapAlloc = HeapAlloc(RefCell::new(Heap::empty()));
+
+/// LockedHeap doesn't locking properly
+struct HeapAlloc(RefCell<Heap>);
+
+/// FIXME: unsound; lock properly
+unsafe impl Sync for HeapAlloc {}
+
+unsafe impl GlobalAlloc for HeapAlloc {
+    unsafe fn alloc(&self, layout: Layout) -> *mut u8 {
+        self.0.borrow_mut()
+            .allocate_first_fit(layout)
+            .ok()
+            .map_or(0 as *mut u8, |allocation| allocation.as_ptr())
+    }
+
+    unsafe fn dealloc(&self, ptr: *mut u8, layout: Layout) {
+        self.0.borrow_mut()
+            .deallocate(NonNull::new_unchecked(ptr), layout)
+    }
+}
+
+pub fn init_alloc(ddr: &mut DdrRam) {
+    unsafe {
+        ALLOCATOR.0.borrow_mut()
+            .init(ddr.ptr::<u8>() as usize, ddr.size());
+    }
+}
+
+
+#[alloc_error_handler]
+fn alloc_error(_: core::alloc::Layout) -> ! {
+    panic!("alloc_error")
+}

src/zynq/axi_hp.rs

@@ -2,7 +2,7 @@
 
 use volatile_register::RW;
 
-use crate::{register, register_bit, register_bits, register_bits_typed};
+use crate::{register, register_bit, register_bits};
 
 pub unsafe fn axi_hp0() -> &'static RegisterBlock {
     &*(0xF8008000 as *const _)

src/zynq/ddr/mod.rs

@@ -186,7 +186,6 @@ impl DdrRam {
         self.regs.mode_sts_reg.read().operating_mode()
     }
 
-    // TODO: move into trait
     pub fn ptr<T>(&mut self) -> *mut T {
         0x0010_0000 as *mut _
     }

src/zynq/ddr/regs.rs

@@ -1,6 +1,6 @@
-use volatile_register::{RO, WO, RW};
+use volatile_register::{RO, RW};
 
-use crate::{register, register_bit, register_bits, register_bits_typed};
+use crate::{register, register_bit, register_bits_typed};
 
 #[repr(u8)]
 pub enum DataBusWidth {
@@ -170,7 +170,8 @@ register_bit!(ddrc_ctrl, powerdown_en, 1);
 register_bits_typed!(ddrc_ctrl, data_bus_width, u8, DataBusWidth, 2, 3);
 // (ddrc_ctrl) ...
 
-/// Controller operation mode status
+// Controller operation mode status
-register!(mode_sts_reg, ModeStsReg, RO, u32);
+register!(mode_sts_reg,
+          ModeStsReg, RO, u32);
 register_bits_typed!(mode_sts_reg, operating_mode, u8, ControllerStatus, 0, 2);
 // (mode_sts_reg) ...

src/zynq/eth/mod.rs

@@ -337,8 +337,17 @@ impl<'r, 'rx, 'tx: 'a, 'a> smoltcp::phy::Device<'a> for &mut Eth<'r, rx::DescLis
     type TxToken = tx::Token<'a, 'tx>;
 
     fn capabilities(&self) -> smoltcp::phy::DeviceCapabilities {
-        let mut caps = smoltcp::phy::DeviceCapabilities::default();
+        use smoltcp::phy::{DeviceCapabilities, ChecksumCapabilities, Checksum};
+
+        let mut checksum_caps = ChecksumCapabilities::default();
+        checksum_caps.ipv4 = Checksum::Both;
+        checksum_caps.tcp = Checksum::Both;
+        checksum_caps.udp = Checksum::Both;
+
+        let mut caps = DeviceCapabilities::default();
         caps.max_transmission_unit = MTU;
+        caps.checksum = checksum_caps;
+
         caps
     }
 
@@ -457,6 +466,8 @@ impl<'r> EthInner<'r> {
                 .copy_all(true)
                 // Remove 4-byte Frame CheckSum
                 .fcs_remove(true)
+                // RX checksum offload
+                .rx_chksum_offld_en(true)
                 // One of the slower speeds
                 .mdc_clk_div((mdc_clk_div >> 4).min(0b111) as u8)
         );
@@ -487,6 +498,7 @@ impl<'r> EthInner<'r> {
                 .rx_pktbuf_memsz_sel(0x3)
                 // 4 KB
                 .tx_pktbuf_memsz_sel(true)
+                // TX checksum offload
                 .csum_gen_offload_en(true)
                 // Little-endian
                 .ahb_endian_swp_mgmt_en(false)