Cargo.toml

@@ -14,6 +14,6 @@ lto = false
 panic = "abort"
 debug = true
 # Link-Time Optimization:
-# turn off if you get unusable debug symbols.
-lto = true
+# turned off for producing unusable debug symbols.
+lto = false
 opt-level = 'z'  # Optimize for size.

experiments/src/ps7_init/mod.rs

@@ -1,5 +1,3 @@
-#![cfg(feature = "target_zc706")]
-
 use libboard_zynq::println;
 
 mod zc706;
@@ -7,8 +5,8 @@ mod zc706;
 
 #[cfg(feature = "target_zc706")]
 use zc706 as target;
-// #[cfg(feature = "target_cora_z7_10")]
-// use cora_z7_10 as target;
+#[cfg(feature = "target_cora_z7_10")]
+use cora_z7_10 as target;
 
 pub fn report_differences() {
     for (i, op) in target::INIT_DATA.iter().enumerate() {

libboard_zynq/src/dmac/regs.rs

@@ -1,3 +1,5 @@
+use volatile_register::{RO, WO, RW};
+
 use libregister::{
     register, register_at,
     register_bit, register_bits, register_bits_typed,

libboard_zynq/src/flash/mod.rs

@@ -328,7 +328,7 @@ impl Flash<()> {
             .mode_bits(0xFF)
             // 2 devices
             .two_mem(true)
-            .u_page(chip_index != 0)
+            .u_page(false)
             // Quad SPI mode
             .lq_mode(false)
         );

libsupport_zynq/src/boot.rs

@@ -142,7 +142,7 @@ impl<S: AsMut<[u32]>> Core1<S> {
         // Ensure stack pointer has been written to cache
         asm::dmb();
         // Flush cache-line
-        cache::dccmvac(unsafe { &CORE1_STACK } as *const _ as usize);
+        cache::dccmvac(unsafe { &CORE1_STACK } as *const _ as u32);
 
         // wake up core1
         slcr::RegisterBlock::unlocked(|slcr| {