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2 Commits
9ee77d8f44
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515d3bb381
Author | SHA1 | Date |
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Astro | 515d3bb381 | |
Astro | 7e22010d7d |
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@ -57,7 +57,7 @@ pub trait ClockSource {
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/// 25.10.4 PLLs
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/// 25.10.4 PLLs
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fn setup(target_freq: u32) {
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fn setup(target_freq: u32) {
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let fdiv = (target_freq / PS_CLK).min(66) as u16;
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let fdiv = (target_freq / PS_CLK).min(66) as u16;
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let (pll_res, pll_cp, lock_cnt) = PLL_FDIV_LOCK_PARAM.iter()
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let (pll_cp, pll_res, lock_cnt) = PLL_FDIV_LOCK_PARAM.iter()
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.filter(|(fdiv_max, _)| fdiv <= *fdiv_max)
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.filter(|(fdiv_max, _)| fdiv <= *fdiv_max)
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.nth(0)
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.nth(0)
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.expect("PLL_FDIV_LOCK_PARAM")
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.expect("PLL_FDIV_LOCK_PARAM")
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@ -44,8 +44,7 @@ impl DdrRam {
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Self::configure_iob();
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Self::configure_iob();
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let regs = regs::RegisterBlock::ddrc();
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let regs = regs::RegisterBlock::ddrc();
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let mut ddr = DdrRam { regs };
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let mut ddr = DdrRam { regs };
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ddr.configure();
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ddr.reset_ddrc(|ddr| ddr.configure());
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ddr.reset_ddrc();
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ddr
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ddr
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}
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}
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}
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}
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@ -319,15 +318,7 @@ impl DdrRam {
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}
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}
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/// Reset DDR controller
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/// Reset DDR controller
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fn reset_ddrc(&mut self) {
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fn reset_ddrc<F: FnMut(&mut Self)>(&mut self, mut f: F) {
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#[cfg(feature = "target_zc706")]
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unsafe {
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// row/column address bits
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self.regs.dram_addr_map_bank.write(0x00000777);
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self.regs.dram_addr_map_col.write(0xFFF00000);
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self.regs.dram_addr_map_row.write(0x0F666666);
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}
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#[cfg(feature = "target_zc706")]
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#[cfg(feature = "target_zc706")]
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let width = regs::DataBusWidth::Width32bit;
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let width = regs::DataBusWidth::Width32bit;
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#[cfg(feature = "target_cora_z7_10")]
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#[cfg(feature = "target_cora_z7_10")]
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@ -339,6 +330,23 @@ impl DdrRam {
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.powerdown_en(false)
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.powerdown_en(false)
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.data_bus_width(width)
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.data_bus_width(width)
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);
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);
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f(self);
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#[cfg(feature = "target_zc706")]
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unsafe {
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// row/column address bits
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self.regs.dram_addr_map_bank.write(0x00000777);
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self.regs.dram_addr_map_col.write(0xFFF00000);
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self.regs.dram_addr_map_row.write(0x0F666666);
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}
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#[cfg(feature = "target_cora_z7_10")]
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unsafe {
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// row/column address bits
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self.regs.dram_addr_map_bank.write(0x00000666);
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self.regs.dram_addr_map_col.write(0xFFFF0000);
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self.regs.dram_addr_map_row.write(0x0F555555);
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}
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self.regs.ddrc_ctrl.modify(|_, w| w
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self.regs.ddrc_ctrl.modify(|_, w| w
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.soft_rstb(true)
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.soft_rstb(true)
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.powerdown_en(false)
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.powerdown_en(false)
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