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zynq-rs
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compare: M-Labs:9ee77d8f448d62057d9a5b8f6afce204a889121f
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No commits in common. "515d3bb381baf3df40b707a6ef173f9e975de182" and "9ee77d8f448d62057d9a5b8f6afce204a889121f" have entirely different histories.
515d3bb381 ... 9ee77d8f44

2 changed files with 12 additions and 20 deletions
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2
libboard_zynq/src/clocks/source.rs
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@ -57,7 +57,7 @@ pub trait ClockSource {
/// 25.10.4 PLLs
fn setup(target_freq: u32) {
let fdiv = (target_freq / PS_CLK).min(66) as u16;
let (pll_cp, pll_res, lock_cnt) = PLL_FDIV_LOCK_PARAM.iter()
let (pll_res, pll_cp, lock_cnt) = PLL_FDIV_LOCK_PARAM.iter()
.filter(|(fdiv_max, _)| fdiv <= *fdiv_max)
.nth(0)
.expect("PLL_FDIV_LOCK_PARAM")

30
libboard_zynq/src/ddr/mod.rs
View File

@ -44,7 +44,8 @@ impl DdrRam {
Self::configure_iob();
let regs = regs::RegisterBlock::ddrc();
let mut ddr = DdrRam { regs };
ddr.reset_ddrc(|ddr| ddr.configure());
ddr.configure();
ddr.reset_ddrc();
ddr
}
}
@ -318,7 +319,15 @@ impl DdrRam {
}
/// Reset DDR controller
fn reset_ddrc<F: FnMut(&mut Self)>(&mut self, mut f: F) {
fn reset_ddrc(&mut self) {
#[cfg(feature = "target_zc706")]
unsafe {
// row/column address bits
self.regs.dram_addr_map_bank.write(0x00000777);
self.regs.dram_addr_map_col.write(0xFFF00000);
self.regs.dram_addr_map_row.write(0x0F666666);
}
#[cfg(feature = "target_zc706")]
let width = regs::DataBusWidth::Width32bit;
#[cfg(feature = "target_cora_z7_10")]
@ -330,23 +339,6 @@ impl DdrRam {
.powerdown_en(false)
.data_bus_width(width)
);
f(self);
#[cfg(feature = "target_zc706")]
unsafe {
// row/column address bits
self.regs.dram_addr_map_bank.write(0x00000777);
self.regs.dram_addr_map_col.write(0xFFF00000);
self.regs.dram_addr_map_row.write(0x0F666666);
}
#[cfg(feature = "target_cora_z7_10")]
unsafe {
// row/column address bits
self.regs.dram_addr_map_bank.write(0x00000666);
self.regs.dram_addr_map_col.write(0xFFFF0000);
self.regs.dram_addr_map_row.write(0x0F555555);
}
self.regs.ddrc_ctrl.modify(|_, w| w
.soft_rstb(true)
.powerdown_en(false)