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0e8354faa1
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500472b2a8
Author | SHA1 | Date |
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Astro | 500472b2a8 | |
Astro | 02217f27d1 | |
Astro | a3eabf1947 | |
Astro | a32d7abb9a |
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@ -36,7 +36,7 @@ let
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"${target}-experiments" = build-crate "${target}-experiments" "experiments" "target_${target}" cargoSha256Experiments;
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"${target}-szl" = build-crate "${target}-szl" "szl" "target_${target}" cargoSha256SZL;
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};
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targets = ["zc706" "coraz7" "redpitaya"];
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targets = ["zc706" "coraz7" "redpitaya" "kasli_soc"];
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in
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{
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inherit cargo-xbuild;
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@ -9,6 +9,7 @@ edition = "2018"
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target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706"]
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target_coraz7 = ["libboard_zynq/target_coraz7", "libsupport_zynq/target_coraz7"]
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target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya"]
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target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc"]
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default = ["target_zc706"]
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[dependencies]
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@ -105,31 +105,20 @@ pub fn main_core0() {
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.boot_mode_pins()
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);
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#[cfg(feature = "target_zc706")]
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#[cfg(any(
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feature = "target_zc706",
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feature = "target_redpitaya",
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feature = "target_kasli_soc",
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))]
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const CPU_FREQ: u32 = 800_000_000;
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#[cfg(feature = "target_coraz7")]
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const CPU_FREQ: u32 = 650_000_000;
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#[cfg(feature = "target_redpitaya")]
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const CPU_FREQ: u32 = 800_000_000;
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info!("Setup clock sources...");
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ArmPll::setup(2 * CPU_FREQ);
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Clocks::set_cpu_freq(CPU_FREQ);
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#[cfg(feature = "target_zc706")]
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{
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IoPll::setup(1_000_000_000);
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libboard_zynq::stdio::drop_uart();
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}
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#[cfg(feature = "target_coraz7")]
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{
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IoPll::setup(1_000_000_000);
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libboard_zynq::stdio::drop_uart();
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}
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#[cfg(feature = "target_redpitaya")]
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{
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IoPll::setup(1_000_000_000);
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libboard_zynq::stdio::drop_uart();
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}
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info!("PLLs set up");
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let clocks = zynq::clocks::Clocks::get();
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info!(
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@ -9,6 +9,7 @@ edition = "2018"
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target_zc706 = []
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target_coraz7 = []
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target_redpitaya = []
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target_kasli_soc = []
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ipv6 = [ "smoltcp/proto-ipv6" ]
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[dependencies]
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@ -8,6 +8,8 @@ pub const PS_CLK: u32 = 33_333_333;
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pub const PS_CLK: u32 = 50_000_000;
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#[cfg(feature = "target_redpitaya")]
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pub const PS_CLK: u32 = 33_333_333;
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#[cfg(feature = "target_kasli_soc")]
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pub const PS_CLK: u32 = 33_333_333;
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/// (pll_fdiv_max, (pll_cp, pll_res, lock_cnt))
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const PLL_FDIV_LOCK_PARAM: &[(u16, (u8, u8, u16))] = &[
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@ -20,8 +20,11 @@ const DDR_FREQ: u32 = 525_000_000;
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/// Alliance Memory AS4C256M16D3B: 800 MHz DDR3 at 533 MHz
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const DDR_FREQ: u32 = 533_333_333;
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/// MT41K256M16HA-125
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const DCI_FREQ: u32 = 10_000_000;
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#[cfg(feature = "target_kasli_soc")]
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/// MT41K256M16HA-125:E: 800 MHz DDR3L at 533 MHz
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const DDR_FREQ: u32 = 533_333_333;
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const DCI_MAX_FREQ: u32 = 10_000_000;
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pub struct DdrRam {
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regs: &'static mut regs::RegisterBlock,
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@ -61,7 +64,7 @@ impl DdrRam {
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}
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fn calculate_dci_divisors(clocks: &Clocks) -> (u8, u8) {
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let target = (DCI_FREQ - 1 + clocks.ddr) / DCI_FREQ;
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let target = (DCI_MAX_FREQ - 1 + clocks.ddr) / DCI_MAX_FREQ;
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let mut best = None;
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let mut best_error = 0;
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@ -144,13 +147,13 @@ impl DdrRam {
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.output_en(slcr::DdriobOutputEn::Obuf);
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#[cfg(feature = "target_zc706")]
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let data1_config = data0_config.clone();
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#[cfg(feature = "target_coraz7")]
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#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
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let data0_config = slcr::DdriobConfig::zeroed()
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.inp_type(slcr::DdriobInputType::VrefDifferential)
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.term_en(true)
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.dci_type(slcr::DdriobDciType::Termination)
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.output_en(slcr::DdriobOutputEn::Obuf);
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#[cfg(feature = "target_coraz7")]
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#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
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let data1_config = slcr::DdriobConfig::zeroed()
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.pullup_en(true);
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#[cfg(feature = "target_redpitaya")]
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@ -173,13 +176,13 @@ impl DdrRam {
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.output_en(slcr::DdriobOutputEn::Obuf);
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#[cfg(feature = "target_zc706")]
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let diff1_config = diff0_config.clone();
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#[cfg(feature = "target_coraz7")]
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#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
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let diff0_config = slcr::DdriobConfig::zeroed()
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.inp_type(slcr::DdriobInputType::Differential)
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.term_en(true)
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.dci_type(slcr::DdriobDciType::Termination)
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.output_en(slcr::DdriobOutputEn::Obuf);
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#[cfg(feature = "target_coraz7")]
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#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
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let diff1_config = slcr::DdriobConfig::zeroed()
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.pullup_en(true);
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#[cfg(feature = "target_redpitaya")]
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@ -207,7 +210,7 @@ impl DdrRam {
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slcr.ddriob_drive_slew_clock.write(0x00F9861C);
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}
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#[cfg(feature = "target_coraz7")]
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#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
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slcr.ddriob_ddr_ctrl.modify(|_, w| w
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.vref_int_en(false)
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.vref_ext_en_lower(true)
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@ -232,7 +235,7 @@ impl DdrRam {
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}
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fn configure(&mut self) {
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#[cfg(feature = "target_coraz7")]
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#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
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self.regs.dram_param0.write(
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regs::DramParam0::zeroed()
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.t_rc(0x1a)
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@ -295,11 +298,11 @@ impl DdrRam {
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.emr(0x4)
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);
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#[cfg(feature = "target_coraz7")]
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#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
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self.regs.phy_configs[2].modify(
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|_, w| w.data_slice_in_use(false)
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);
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#[cfg(feature = "target_coraz7")]
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#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
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self.regs.phy_configs[3].modify(
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|_, w| w.data_slice_in_use(false)
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);
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@ -351,7 +354,7 @@ impl DdrRam {
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.gatelvl_init_ratio(0xee)
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);
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#[cfg(feature = "target_coraz7")]
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#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
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self.regs.reg_64.modify(
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|_, w| w
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.phy_ctrl_slave_ratio(0x100)
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@ -387,7 +390,7 @@ impl DdrRam {
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fn reset_ddrc<F: FnMut(&mut Self)>(&mut self, mut f: F) {
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#[cfg(feature = "target_zc706")]
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let width = regs::DataBusWidth::Width32bit;
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#[cfg(feature = "target_coraz7")]
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#[cfg(any(feature = "target_coraz7", feature = "target_kasli_soc"))]
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let width = regs::DataBusWidth::Width16bit;
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#[cfg(feature = "target_redpitaya")]
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let width = regs::DataBusWidth::Width16bit;
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@ -405,7 +408,11 @@ impl DdrRam {
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self.regs.dram_addr_map_col.write(0xFFF00000);
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self.regs.dram_addr_map_row.write(0x0F666666);
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}
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#[cfg(any(feature = "target_coraz7", feature = "target_redpitaya"))]
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#[cfg(any(
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feature = "target_coraz7",
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feature = "target_redpitaya",
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feature = "target_kasli_soc",
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))]
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unsafe {
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// row/column address bits
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self.regs.dram_addr_map_bank.write(0x00000666);
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@ -437,9 +444,11 @@ impl DdrRam {
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// filtering address map
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#[cfg(feature = "target_zc706")]
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let megabytes = 1023;
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#[cfg(feature = "target_coraz7")]
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let megabytes = 512;
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#[cfg(feature = "target_redpitaya")]
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#[cfg(any(
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feature = "target_coraz7",
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feature = "target_redpitaya",
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feature = "target_kasli_soc",
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))]
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let megabytes = 512;
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megabytes * 1024 * 1024
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@ -117,7 +117,7 @@ impl Sdio {
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);
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}
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// redpitaya card detect pin
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#[cfg(feature = "target_redpitaya")]
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#[cfg(any(feature = "target_redpitaya", feature = "target_kasli_soc"))]
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{
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unsafe {
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slcr.sd0_wp_cd_sel.write(46 << 16);
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@ -47,7 +47,7 @@ impl DerefMut for LazyUart {
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LazyUart::Uninitialized => {
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#[cfg(any(feature = "target_coraz7", feature = "target_redpitaya"))]
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let uart = Uart::uart0(UART_RATE);
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#[cfg(feature = "target_zc706")]
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#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
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let uart = Uart::uart1(UART_RATE);
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*self = LazyUart::Initialized(uart);
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self
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@ -46,7 +46,7 @@ impl Uart {
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self_
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}
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#[cfg(feature = "target_zc706")]
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#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))]
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pub fn uart1(baudrate: u32) -> Self {
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slcr::RegisterBlock::unlocked(|slcr| {
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// Route UART 1 RxD/TxD Signals to MIO Pins
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@ -14,4 +14,5 @@ log = "0.4"
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target_zc706 = []
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target_coraz7 = []
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target_redpitaya = []
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target_kasli_soc = []
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ipv6 = []
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@ -43,6 +43,10 @@ pub fn get_adresses(cfg: &Config) -> NetAddresses {
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let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x55]);
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#[cfg(feature = "target_redpitaya")]
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let mut ipv4_addr = IpAddress::v4(192, 168, 1, 55);
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#[cfg(feature = "target_kasli_soc")]
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let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x56]);
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#[cfg(feature = "target_kasli_soc")]
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let mut ipv4_addr = IpAddress::v4(192, 168, 1, 56);
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if let Ok(Ok(addr)) = cfg.read_str("mac").map(|s| s.parse()) {
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hardware_addr = addr;
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@ -5,11 +5,8 @@ authors = ["M-Labs"]
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edition = "2018"
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[features]
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target_zc706 = []
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target_coraz7 = []
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target_redpitaya = []
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power_saving = []
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default = ["target_zc706"]
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default = []
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[dependencies]
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bit_field = "0.10"
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@ -9,6 +9,7 @@ edition = "2018"
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target_zc706 = ["libboard_zynq/target_zc706"]
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target_coraz7 = ["libboard_zynq/target_coraz7"]
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target_redpitaya = ["libboard_zynq/target_redpitaya"]
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target_kasli_soc = ["libboard_zynq/target_kasli_soc"]
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panic_handler = []
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dummy_irq_handler = []
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alloc_core = []
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@ -9,6 +9,7 @@ edition = "2018"
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target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706", "libconfig/target_zc706"]
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target_coraz7 = ["libboard_zynq/target_coraz7", "libsupport_zynq/target_coraz7", "libconfig/target_coraz7"]
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target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya", "libconfig/target_redpitaya"]
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target_kasli_soc = ["libboard_zynq/target_kasli_soc", "libsupport_zynq/target_kasli_soc", "libconfig/target_kasli_soc"]
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default = ["target_zc706"]
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[dependencies]
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