From f9cb2e7cb02d6f96d8955cf74882d018bda7cfd5 Mon Sep 17 00:00:00 2001 From: Astro Date: Thu, 30 Jan 2020 23:18:14 +0100 Subject: [PATCH] delint --- libboard_zynq/src/clocks/mod.rs | 2 +- libboard_zynq/src/devc/mod.rs | 2 -- libboard_zynq/src/devc/regs.rs | 2 -- libboard_zynq/src/flash/mod.rs | 14 -------------- 4 files changed, 1 insertion(+), 19 deletions(-) diff --git a/libboard_zynq/src/clocks/mod.rs b/libboard_zynq/src/clocks/mod.rs index eea0f11..fef755a 100644 --- a/libboard_zynq/src/clocks/mod.rs +++ b/libboard_zynq/src/clocks/mod.rs @@ -1,4 +1,4 @@ -use libregister::{RegisterR, RegisterW, RegisterRW}; +use libregister::{RegisterR, RegisterRW}; use super::slcr; pub use slcr::ArmPllSource; diff --git a/libboard_zynq/src/devc/mod.rs b/libboard_zynq/src/devc/mod.rs index 39fc68e..ba4e98f 100644 --- a/libboard_zynq/src/devc/mod.rs +++ b/libboard_zynq/src/devc/mod.rs @@ -1,5 +1,3 @@ -use core::fmt; - use libregister::*; mod regs; diff --git a/libboard_zynq/src/devc/regs.rs b/libboard_zynq/src/devc/regs.rs index b8a0f0e..15c1c42 100644 --- a/libboard_zynq/src/devc/regs.rs +++ b/libboard_zynq/src/devc/regs.rs @@ -1,5 +1,3 @@ -use volatile_register::{RO, WO, RW}; - use libregister::{ register, register_at, register_bit, register_bits, register_bits_typed, diff --git a/libboard_zynq/src/flash/mod.rs b/libboard_zynq/src/flash/mod.rs index d3e34b3..e53d7d7 100644 --- a/libboard_zynq/src/flash/mod.rs +++ b/libboard_zynq/src/flash/mod.rs @@ -29,8 +29,6 @@ const INST_WRDI: u8 = 0x04; const INST_WREN: u8 = 0x06; /// Instruction: Program page const INST_PP: u8 = 0x02; -/// Instruction: Sector Erase -const INST_SE: u8 = 0xD8; /// Instruction: Erase 4K Block const INST_BE_4K: u8 = 0x20; @@ -93,18 +91,6 @@ impl Flash { ); } - fn enable_interrupts(&mut self) { - self.regs.intr_en.write( - regs::IntrEn::zeroed() - .rx_overflow(true) - .tx_fifo_not_full(true) - .tx_fifo_full(true) - .rx_fifo_not_empty(true) - .rx_fifo_full(true) - .tx_fifo_underflow(true) - ); - } - fn clear_rx_fifo(&self) { while self.regs.intr_status.read().rx_fifo_not_empty() { let _ = self.regs.rx_data.read();