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zynq-rs
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pull/29/head
Astro 2020-01-30 23:18:14 +01:00
parent 2b543c18c5
commit f9cb2e7cb0
4 changed files with 1 additions and 19 deletions
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2
libboard_zynq/src/clocks/mod.rs
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@ -1,4 +1,4 @@
use libregister::{RegisterR, RegisterW, RegisterRW};
use libregister::{RegisterR, RegisterRW};
use super::slcr;
pub use slcr::ArmPllSource;

2
libboard_zynq/src/devc/mod.rs
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@ -1,5 +1,3 @@
use core::fmt;
use libregister::*;
mod regs;

2
libboard_zynq/src/devc/regs.rs
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@ -1,5 +1,3 @@
use volatile_register::{RO, WO, RW};
use libregister::{
register, register_at,
register_bit, register_bits, register_bits_typed,

14
libboard_zynq/src/flash/mod.rs
View File

@ -29,8 +29,6 @@ const INST_WRDI: u8 = 0x04;
const INST_WREN: u8 = 0x06;
/// Instruction: Program page
const INST_PP: u8 = 0x02;
/// Instruction: Sector Erase
const INST_SE: u8 = 0xD8;
/// Instruction: Erase 4K Block
const INST_BE_4K: u8 = 0x20;
@ -93,18 +91,6 @@ impl<MODE> Flash<MODE> {
);
}
fn enable_interrupts(&mut self) {
self.regs.intr_en.write(
regs::IntrEn::zeroed()
.rx_overflow(true)
.tx_fifo_not_full(true)
.tx_fifo_full(true)
.rx_fifo_not_empty(true)
.rx_fifo_full(true)
.tx_fifo_underflow(true)
);
}
fn clear_rx_fifo(&self) {
while self.regs.intr_status.read().rx_fifo_not_empty() {
let _ = self.regs.rx_data.read();