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zynq-rs
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eth: add const MTU

This commit is contained in:
Astro 2019-06-22 01:34:17 +02:00
parent 6757ceb76c
commit ec5dda4d0a
2 changed files with 10 additions and 6 deletions
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11
src/eth/mod.rs
View File

@ -6,6 +6,9 @@ mod regs;
pub mod rx; pub mod rx;
pub mod tx; pub mod tx;
/// Size of all the buffers
pub const MTU: usize = 1536;
pub struct Eth<RX, TX> { pub struct Eth<RX, TX> {
regs: &'static mut regs::RegisterBlock, regs: &'static mut regs::RegisterBlock,
rx: RX, rx: RX,
@ -295,7 +298,7 @@ impl<RX, TX> Eth<RX, TX> {
self.regs.dma_cfg.write( self.regs.dma_cfg.write(
regs::DmaCfg::zeroed() regs::DmaCfg::zeroed()
// 1536 bytes // 1536 bytes
.ahb_mem_rx_buf_size(0x18) .ahb_mem_rx_buf_size((MTU >> 6) as u8)
// 8 KB // 8 KB
.rx_pktbuf_memsz_sel(0x3) .rx_pktbuf_memsz_sel(0x3)
// 4 KB // 4 KB
@ -313,10 +316,10 @@ impl<RX, TX> Eth<RX, TX> {
); );
} }
pub fn start_rx<'rx>(self, list: &'rx mut [rx::DescEntry], rx_buffers: &'rx mut [[u8; 1536]]) -> Eth<rx::DescList<'rx>, TX> { pub fn start_rx<'rx>(self, rx_list: &'rx mut [rx::DescEntry], rx_buffers: &'rx mut [[u8; MTU]]) -> Eth<rx::DescList<'rx>, TX> {
let new_self = Eth { let new_self = Eth {
regs: self.regs, regs: self.regs,
rx: rx::DescList::new(list, rx_buffers), rx: rx::DescList::new(rx_list, rx_buffers),
tx: self.tx, tx: self.tx,
}; };
let list_addr = new_self.rx.list_addr(); let list_addr = new_self.rx.list_addr();
@ -355,7 +358,7 @@ impl<RX, TX> Eth<RX, TX> {
} }
impl<'rx, TX> Eth<rx::DescList<'rx>, TX> { impl<'rx, TX> Eth<rx::DescList<'rx>, TX> {
pub fn recv_next(&mut self) -> Result<Option<rx::PktRef>, rx::Error> { pub fn recv_next<'s: 'p, 'p>(&'s mut self) -> Result<Option<rx::PktRef<'p>>, rx::Error> {
let status = self.regs.rx_status.read(); let status = self.regs.rx_status.read();
if status.hresp_not_ok() { if status.hresp_not_ok() {
// Clear // Clear

5
src/eth/rx.rs
View File

@ -1,5 +1,6 @@
use core::ops::Deref; use core::ops::Deref;
use crate::{register, register_bit, register_bits, register_bits_typed, regs::*}; use crate::{register, register_bit, register_bits, register_bits_typed, regs::*};
use super::MTU;
#[derive(Debug)] #[derive(Debug)]
pub enum Error { pub enum Error {
@ -43,12 +44,12 @@ register_bit!(desc_word1, global_broadcast, 31);
#[repr(C)] #[repr(C)]
pub struct DescList<'a> { pub struct DescList<'a> {
list: &'a mut [DescEntry], list: &'a mut [DescEntry],
buffers: &'a mut [[u8; 1536]], buffers: &'a mut [[u8; MTU]],
next: usize, next: usize,
} }
impl<'a> DescList<'a> { impl<'a> DescList<'a> {
pub fn new(list: &'a mut [DescEntry], buffers: &'a mut [[u8; 1536]]) -> Self { pub fn new(list: &'a mut [DescEntry], buffers: &'a mut [[u8; MTU]]) -> Self {
let last = list.len().min(buffers.len()) - 1; let last = list.len().min(buffers.len()) - 1;
for (i, (entry, buffer)) in list.iter_mut().zip(buffers.iter_mut()).enumerate() { for (i, (entry, buffer)) in list.iter_mut().zip(buffers.iter_mut()).enumerate() {
let is_last = i == last; let is_last = i == last;