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zynq-rs
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eth: fix cache maintenance

This commit is contained in:
Astro 2020-06-22 02:43:22 +02:00
parent 77c3998dbd
commit cd8abae839
3 changed files with 8 additions and 16 deletions
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2
experiments/src/main.rs
View File

@ -252,7 +252,7 @@ if false {
while let Ok(stream) = TcpStream::accept(TCP_PORT, 0x10_0000, 0x10_0000).await { while let Ok(stream) = TcpStream::accept(TCP_PORT, 0x10_0000, 0x10_0000).await {
let stats_tx = stats_tx.clone(); let stats_tx = stats_tx.clone();
task::spawn(async move { task::spawn(async move {
let tx_data = (0..=255).take(4096).collect::<alloc::vec::Vec<u8>>(); let tx_data = (0..=255).take(65536).collect::<alloc::vec::Vec<u8>>();
loop { loop {
// const CHUNK_SIZE: usize = 65536; // const CHUNK_SIZE: usize = 65536;
// match stream.send((0..=255).cycle().take(CHUNK_SIZE)).await { // match stream.send((0..=255).cycle().take(CHUNK_SIZE)).await {

13
libboard_zynq/src/eth/rx.rs
View File

@ -83,10 +83,6 @@ impl DescList {
entry.word1.write( entry.word1.write(
DescWord1::zeroed() DescWord1::zeroed()
); );
// Flush buffer from cache, to be filled by the peripheral
// before next read
l2cache().clean_invalidate_slice(&buffer[..]);
dcci_slice(&buffer[..]);
} }
DescList { DescList {
@ -108,8 +104,9 @@ impl DescList {
let word1 = entry.word1.read(); let word1 = entry.word1.read();
let len = word1.frame_length_lsbs().into(); let len = word1.frame_length_lsbs().into();
let buffer = &mut self.buffers[self.next][0..len]; let buffer = &mut self.buffers[self.next][0..len];
// l2cache().invalidate_slice(&mut buffer[..]); // Invalidate caches for packet buffer
// dcci_slice(&buffer[..]); l2cache().invalidate_slice(&mut buffer[..]);
dcci_slice(&buffer[..]);
self.next += 1; self.next += 1;
if self.next >= list_len { if self.next >= list_len {
@ -138,10 +135,6 @@ pub struct PktRef<'a> {
impl<'a> Drop for PktRef<'a> { impl<'a> Drop for PktRef<'a> {
fn drop(&mut self) { fn drop(&mut self) {
// Flush buffer from cache, to be filled by the peripheral
// before next read
l2cache().invalidate_slice(self.buffer);
dcci_slice(self.buffer);
self.entry.word0.modify(|_, w| w.used(false)); self.entry.word0.modify(|_, w| w.used(false));
dmb(); dmb();

9
libboard_zynq/src/eth/tx.rs
View File

@ -1,6 +1,6 @@
use core::ops::{Deref, DerefMut}; use core::ops::{Deref, DerefMut};
use alloc::{vec, vec::Vec}; use alloc::{vec, vec::Vec};
use libcortex_a9::{cache::dcc_slice, UncachedSlice}; use libcortex_a9::{asm::dmb, cache::dcc_slice, UncachedSlice};
use libregister::*; use libregister::*;
use log::{debug, warn}; use log::{debug, warn};
use crate::l2cache; use crate::l2cache;
@ -95,7 +95,7 @@ impl DescList {
// debug!("send {}", length); // debug!("send {}", length);
let list_len = self.list.len(); let list_len = self.list.len();
let entry = &mut self.list[self.next]; let entry = &mut self.list[self.next];
// dmb(); dmb();
if entry.word1.read().used() { if entry.word1.read().used() {
let buffer = &mut self.buffers[self.next][0..length]; let buffer = &mut self.buffers[self.next][0..length];
entry.word1.write(DescWord1::zeroed() entry.word1.write(DescWord1::zeroed()
@ -129,13 +129,12 @@ pub struct PktRef<'a> {
impl<'a> Drop for PktRef<'a> { impl<'a> Drop for PktRef<'a> {
fn drop(&mut self) { fn drop(&mut self) {
// Write back all dirty cachelines of this buffer // Write back all dirty cachelines of packet buffer
dcc_slice(self.buffer); dcc_slice(self.buffer);
l2cache().clean_slice(self.buffer); l2cache().clean_slice(self.buffer);
self.entry.word1.modify(|_, w| w.used(false)); self.entry.word1.modify(|_, w| w.used(false));
// dcci(self.entry); dmb();
// l2cache().clean_invalidate(self.entry);
// dsb(); // dsb();
if ! self.regs.tx_status.read().tx_go() { if ! self.regs.tx_status.read().tx_go() {
// Start TX if not already running // Start TX if not already running