diff --git a/libboard_zynq/src/i2c/eeprom.rs b/libboard_zynq/src/i2c/eeprom.rs index a90670e..2507cbd 100644 --- a/libboard_zynq/src/i2c/eeprom.rs +++ b/libboard_zynq/src/i2c/eeprom.rs @@ -4,6 +4,7 @@ use embedded_hal::timer::CountDown; pub struct EEPROM<'a> { i2c: &'a mut I2c, + #[cfg(not(feature = "target_ebaz4205"))] port: u8, address: u8, page_size: u8, @@ -46,6 +47,11 @@ impl<'a> EEPROM<'a> { Ok(()) } + #[cfg(feature = "target_ebaz4205")] + fn select(&mut self) -> Result<(), &'static str> { + Ok(()) + } + /// Random read pub fn read<'r>(&mut self, addr: u8, buf: &'r mut [u8]) -> Result<(), &'static str> { self.select()?; diff --git a/libboard_zynq/src/i2c/mod.rs b/libboard_zynq/src/i2c/mod.rs index de1eb7c..9a3cc51 100644 --- a/libboard_zynq/src/i2c/mod.rs +++ b/libboard_zynq/src/i2c/mod.rs @@ -2,10 +2,13 @@ mod regs; pub mod eeprom; +#[cfg(not(feature = "target_ebaz4205"))] use super::slcr; use super::time::Microseconds; use embedded_hal::timer::CountDown; -use libregister::{RegisterR, RegisterRW, RegisterW}; +use libregister::{RegisterR, RegisterRW}; +#[cfg(not(feature = "target_ebaz4205"))] +use libregister::RegisterW; #[cfg(feature = "target_kasli_soc")] use log::info; @@ -22,9 +25,10 @@ pub struct I2c { } impl I2c { - #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] + #[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))] pub fn i2c0() -> Self { // Route I2C 0 SCL / SDA Signals to MIO Pins 50 / 51 + #[cfg(not(feature = "target_ebaz4205"))] slcr::RegisterBlock::unlocked(|slcr| { // SCL slcr.mio_pin_50.write( diff --git a/libboard_zynq/src/i2c/regs.rs b/libboard_zynq/src/i2c/regs.rs index 7d566fd..6fac191 100644 --- a/libboard_zynq/src/i2c/regs.rs +++ b/libboard_zynq/src/i2c/regs.rs @@ -21,6 +21,7 @@ use libregister::{ // Current compatibility: // zc706: GPIO 50, 51 == SCL, SDA // kasli_soc: GPIO 50, 51 == SCL, SDA; GPIO 33 == I2C_SW_RESET +// ebaz4205: GPIO (EMIO) pub struct RegisterBlock { pub gpio_output_mask: &'static mut GPIOOutputMask, @@ -48,17 +49,17 @@ register!(gpio_output_mask, /// MASK_DATA_1_MSW: /// Maskable output data for MIO[53:48] GPIOOutputMask, RW, u32); -#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] +#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))] register_at!(GPIOOutputMask, 0xE000A00C, new); -#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] +#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))] register_bit!(gpio_output_mask, /// Output for SCL scl_o, 2); -#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] +#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))] register_bit!(gpio_output_mask, /// Output for SDA sda_o, 3); -#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] +#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))] register_bits!(gpio_output_mask, /// Mask for keeping bits except SCL and SDA unchanged mask, u16, 16, 31); @@ -82,13 +83,13 @@ register!(gpio_input, /// DATA_1_RO: /// Input data for MIO[53:32] GPIOInput, RO, u32); -#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] +#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))] register_at!(GPIOInput, 0xE000A064, new); -#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] +#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))] register_bit!(gpio_input, /// Input for SCL scl, 18); -#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] +#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))] register_bit!(gpio_input, /// Input for SDA sda, 19); @@ -98,13 +99,13 @@ register!(gpio_direction, /// DIRM_1: /// Direction mode for MIO[53:32]; 0/1 = in/out GPIODirection, RW, u32); -#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] +#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))] register_at!(GPIODirection, 0xE000A244, new); -#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] +#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))] register_bit!(gpio_direction, /// Direction for SCL scl, 18); -#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] +#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))] register_bit!(gpio_direction, /// Direction for SDA sda, 19); @@ -117,13 +118,13 @@ register!(gpio_output_enable, /// OEN_1: /// Output enable for MIO[53:32] GPIOOutputEnable, RW, u32); -#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] +#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))] register_at!(GPIOOutputEnable, 0xE000A248, new); -#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] +#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))] register_bit!(gpio_output_enable, /// Output enable for SCL scl, 18); -#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] +#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))] register_bit!(gpio_output_enable, /// Output enable for SDA sda, 19); diff --git a/libboard_zynq/src/lib.rs b/libboard_zynq/src/lib.rs index 14c6e99..c9a9adb 100644 --- a/libboard_zynq/src/lib.rs +++ b/libboard_zynq/src/lib.rs @@ -19,7 +19,7 @@ pub mod gic; pub mod time; pub mod timer; pub mod sdio; -#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc"))] +#[cfg(any(feature = "target_zc706", feature = "target_kasli_soc", feature = "target_ebaz4205"))] pub mod i2c; pub mod logger; pub mod ps7_init;