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zynq-rs
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fix wrong core target config

This commit is contained in:
morgan 2023-12-19 17:13:18 +08:00
parent a43b8bf64e
commit 99ad16bfc1
1 changed files with 1 additions and 1 deletions
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2
libboard_zynq/src/gic.rs
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@ -115,7 +115,7 @@ impl InterruptController {
let m = (id.0 >> 2) as usize; let m = (id.0 >> 2) as usize;
let n = (8 * (id.0 & 3)) as usize; let n = (8 * (id.0 & 3)) as usize;
unsafe { unsafe {
self.mpcore.icdiptr[m].modify(|mut icdiptr| *icdiptr.set_bits(n..=n+1, target_cpu as u32 + 1)); self.mpcore.icdiptr[m].modify(|mut icdiptr| *icdiptr.set_bits(n..=n+1, target_cpu as u32));
} }
// sensitivity // sensitivity