fix wrong core target config

2023-12-19 17:13:18 +08:00 · 2023-12-19 17:13:18 +08:00 · 99ad16bfc1
parent a43b8bf64e
commit 99ad16bfc1
1 changed files with 1 additions and 1 deletions
--- a/libboard_zynq/src/gic.rs
+++ b/libboard_zynq/src/gic.rs
@ -115,7 +115,7 @@ impl InterruptController {
        let m = (id.0 >> 2) as usize;
        let n = (8 * (id.0 & 3)) as usize;
        unsafe {
-            self.mpcore.icdiptr[m].modify(|mut icdiptr| *icdiptr.set_bits(n..=n+1, target_cpu as u32 + 1));
+            self.mpcore.icdiptr[m].modify(|mut icdiptr| *icdiptr.set_bits(n..=n+1, target_cpu as u32));
        }

        // sensitivity