gic: start implementation
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d18021fc5c
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96b16d2c6c
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@ -0,0 +1,74 @@
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//! ARM Generic Interrupt Controller
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use bit_field::BitField;
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use libregister::{RegisterW, RegisterRW};
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use super::mpcore;
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#[derive(Debug, Clone, Copy)]
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pub struct InterruptId(u8);
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#[derive(Debug, Clone, Copy)]
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pub enum InterruptSensitivity {
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Level,
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Edge,
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}
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pub struct InterruptController {
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mpcore: mpcore::RegisterBlock,
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}
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impl InterruptController {
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pub fn new(mpcore: mpcore::RegisterBlock) -> Self {
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InterruptController { mpcore }
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}
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pub fn disable_interrupts(&mut self) {
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self.mpcore.iccicr.modify(|_, w| w.enable_ns(false)
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.enable_s(false));
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self.mpcore.icddcr.modify(|_, w| w.enable_secure(false)
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.enable_non_secure(false));
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}
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/// enable interrupt signaling
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pub fn enable_interrupts(&mut self) {
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self.mpcore.iccicr.modify(|_, w| w.enable_ns(true)
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.enable_s(true));
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self.mpcore.icddcr.modify(|_, w| w.enable_secure(true));
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}
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pub fn enable(&mut self, id: InterruptId, target_cpu: u32, sensitivity: InterruptSensitivity) {
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assert!(target_cpu < 2);
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self.disable_interrupts();
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// enable
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let m = (id.0 >> 5) as usize;
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let n = (id.0 & 0x1F) as usize;
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assert!(m < 3);
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unsafe {
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self.mpcore.icdiser[m].modify(|mut icdiser| *icdiser.set_bit(n, true));
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}
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// target cpu
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let m = (id.0 >> 2) as usize;
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let n = (8 * (id.0 & 3)) as usize;
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unsafe {
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self.mpcore.icdiptr[m].modify(|mut icdiptr| *icdiptr.set_bits(n..=n+1, target_cpu + 1));
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}
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// sensitivity
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let m = (id.0 >> 4) as usize;
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let n = (2 * (id.0 & 0xF)) as usize;
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unsafe {
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self.mpcore.icdicfr[m].modify(|mut icdicfr| *icdicfr.set_bits(n..=n+1, match sensitivity {
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InterruptSensitivity::Level => 0b00,
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InterruptSensitivity::Edge => 0b10,
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}));
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}
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// filter no interrupts (lowest priority)
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self.mpcore.iccpmr.write(mpcore::ICCPMR::zeroed().priority(0xFF));
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self.enable_interrupts();
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}
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}
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@ -15,6 +15,7 @@ pub mod axi_hp;
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pub mod axi_gp;
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pub mod axi_gp;
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pub mod ddr;
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pub mod ddr;
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pub mod mpcore;
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pub mod mpcore;
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pub mod gic;
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pub mod flash;
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pub mod flash;
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pub mod time;
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pub mod time;
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pub mod timer;
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pub mod timer;
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@ -93,12 +93,8 @@ pub struct RegisterBlock {
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pub icdisr1: RW<u32>,
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pub icdisr1: RW<u32>,
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pub icdisr2: RW<u32>,
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pub icdisr2: RW<u32>,
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unused8: [u32; 29],
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unused8: [u32; 29],
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/// Interrupt Set-enable Register 0
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/// Interrupt Set-enable Registers
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pub icdiser0: RW<u32>,
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pub icdiser: [RW<u32>; 3],
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/// Interrupt Set-enable Register 1
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pub icdiser1: RW<u32>,
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/// Interrupt Set-enable Register 2
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pub icdiser2: RW<u32>,
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unused9: [u32; 29],
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unused9: [u32; 29],
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/// Interrupt Clear-Enable Register 0
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/// Interrupt Clear-Enable Register 0
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pub icdicer0: RW<u32>,
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pub icdicer0: RW<u32>,
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@ -148,67 +144,11 @@ pub struct RegisterBlock {
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pub icdipr22: RW<u32>,
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pub icdipr22: RW<u32>,
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pub icdipr23: RW<u32>,
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pub icdipr23: RW<u32>,
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unused14: [u32; 232],
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unused14: [u32; 232],
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/// Interrupt Processor Targets Register 0
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/// Interrupt Processor Targets Registers
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pub icdiptr0: ICDIPTR0,
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pub icdiptr: [RW<u32>; 24],
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/// Interrupt Processor Targets Register 1
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pub icdiptr1: ICDIPTR1,
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/// Interrupt Processor Targets Register 2
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pub icdiptr2: ICDIPTR2,
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/// Interrupt Processor Targets Register 3
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pub icdiptr3: ICDIPTR3,
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/// Interrupt Processor Targets Register 4
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pub icdiptr4: RW<u32>,
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/// Interrupt Processor Targets Register 5
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pub icdiptr5: RO<u32>,
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/// Interrupt Processor Targets Register 6
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pub icdiptr6: ICDIPTR6,
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/// Interrupt Processor Targets Register 7
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pub icdiptr7: ICDIPTR7,
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/// Interrupt Processor Targets Register 8
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pub icdiptr8: ICDIPTR8,
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/// Interrupt Processor Targets Register 9
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pub icdiptr9: ICDIPTR9,
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/// Interrupt Processor Targets Register 10
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pub icdiptr10: ICDIPTR10,
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/// Interrupt Processor Targets Register 11
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pub icdiptr11: ICDIPTR11,
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/// Interrupt Processor Targets Register 12
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pub icdiptr12: ICDIPTR12,
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/// Interrupt Processor Targets Register 13
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pub icdiptr13: ICDIPTR13,
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/// Interrupt Processor Targets Register 14
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pub icdiptr14: ICDIPTR14,
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/// Interrupt Processor Targets Register 15
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pub icdiptr15: ICDIPTR15,
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/// Interrupt Processor Targets Register 16
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pub icdiptr16: ICDIPTR16,
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/// Interrupt Processor Targets Register 17
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pub icdiptr17: ICDIPTR17,
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/// Interrupt Processor Targets Register 18
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pub icdiptr18: ICDIPTR18,
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/// Interrupt Processor Targets Register 19
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pub icdiptr19: ICDIPTR19,
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/// Interrupt Processor Targets Register 20
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pub icdiptr20: ICDIPTR20,
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/// Interrupt Processor Targets Register 21
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pub icdiptr21: ICDIPTR21,
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/// Interrupt Processor Targets Register 22
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pub icdiptr22: ICDIPTR22,
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/// Interrupt Processor Targets Register 23
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pub icdiptr23: ICDIPTR23,
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unused15: [u32; 232],
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unused15: [u32; 232],
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/// Interrupt Configuration Register 0
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/// Interrupt Configuration Registers
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pub icdicfr0: ICDICFR0,
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pub icdicfr: [RW<u32>; 6],
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/// Interrupt Configuration Register 1
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pub icdicfr1: ICDICFR1,
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/// Interrupt Configuration Register 2
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pub icdicfr2: ICDICFR2,
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/// Interrupt Configuration Register 3
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pub icdicfr3: ICDICFR3,
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/// Interrupt Configuration Register 4
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pub icdicfr4: ICDICFR4,
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/// Interrupt Configuration Register 5
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pub icdicfr5: ICDICFR5,
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unused16: [u32; 58],
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unused16: [u32; 58],
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/// PPI Status Register
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/// PPI Status Register
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pub ppi_status: PpiStatus,
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pub ppi_status: PpiStatus,
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@ -391,232 +331,6 @@ register_bits!(icdiidr, implementation_version, u8, 24, 31);
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register_bits!(icdiidr, revision_number, u32, 12, 23);
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register_bits!(icdiidr, revision_number, u32, 12, 23);
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register_bits!(icdiidr, implementer, u32, 0, 11);
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register_bits!(icdiidr, implementer, u32, 0, 11);
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register!(icdipt_r0, ICDIPTR0, RO, u32);
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register_bits!(icdipt_r0, target_3, u8, 24, 25);
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register_bits!(icdipt_r0, target_2, u8, 16, 17);
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register_bits!(icdipt_r0, target_1, u8, 8, 9);
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register_bits!(icdipt_r0, target_0, u8, 0, 1);
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register!(icdipt_r1, ICDIPTR1, RO, u32);
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register_bits!(icdipt_r1, target_7, u8, 24, 25);
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register_bits!(icdipt_r1, target_6, u8, 16, 17);
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register_bits!(icdipt_r1, target_5, u8, 8, 9);
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register_bits!(icdipt_r1, target_4, u8, 0, 1);
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register!(icdipt_r2, ICDIPTR2, RO, u32);
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register_bits!(icdipt_r2, target_11, u8, 24, 25);
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register_bits!(icdipt_r2, target_10, u8, 16, 17);
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register_bits!(icdipt_r2, target_9, u8, 8, 9);
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register_bits!(icdipt_r2, target_8, u8, 0, 1);
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register!(icdipt_r3, ICDIPTR3, RO, u32);
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register_bits!(icdipt_r3, target_15, u8, 24, 25);
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register_bits!(icdipt_r3, target_14, u8, 16, 17);
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register_bits!(icdipt_r3, target_13, u8, 8, 9);
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register_bits!(icdipt_r3, target_12, u8, 0, 1);
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register!(icdipt_r6, ICDIPTR6, RO, u32);
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register_bits!(icdipt_r6, target_27, u8, 24, 25);
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register!(icdipt_r7, ICDIPTR7, RO, u32);
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register_bits!(icdipt_r7, target_31, u8, 24, 25);
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register_bits!(icdipt_r7, target_30, u8, 16, 17);
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register_bits!(icdipt_r7, target_29, u8, 8, 9);
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register_bits!(icdipt_r7, target_28, u8, 0, 1);
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register!(icdipt_r8, ICDIPTR8, RW, u32);
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register_bits!(icdipt_r8, target_35, u8, 24, 25);
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register_bits!(icdipt_r8, target_34, u8, 16, 17);
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register_bits!(icdipt_r8, target_33, u8, 8, 9);
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register_bits!(icdipt_r8, target_32, u8, 0, 1);
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register!(icdipt_r9, ICDIPTR9, RW, u32);
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register_bits!(icdipt_r9, target_39, u8, 24, 25);
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register_bits!(icdipt_r9, target_38, u8, 16, 17);
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register_bits!(icdipt_r9, target_37, u8, 8, 9);
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register_bits!(icdipt_r9, target_36, u8, 0, 1);
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register!(icdipt_r10, ICDIPTR10, RW, u32);
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register_bits!(icdipt_r10, target_43, u8, 24, 25);
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register_bits!(icdipt_r10, target_42, u8, 16, 17);
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register_bits!(icdipt_r10, target_41, u8, 8, 9);
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register_bits!(icdipt_r10, target_40, u8, 0, 1);
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register!(icdipt_r11, ICDIPTR11, RW, u32);
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register_bits!(icdipt_r11, target_47, u8, 24, 25);
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register_bits!(icdipt_r11, target_46, u8, 16, 17);
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register_bits!(icdipt_r11, target_45, u8, 8, 9);
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register_bits!(icdipt_r11, target_44, u8, 0, 1);
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register!(icdipt_r12, ICDIPTR12, RW, u32);
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register_bits!(icdipt_r12, target_51, u8, 24, 25);
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register_bits!(icdipt_r12, target_50, u8, 16, 17);
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register_bits!(icdipt_r12, target_49, u8, 8, 9);
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register_bits!(icdipt_r12, target_48, u8, 0, 1);
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register!(icdipt_r13, ICDIPTR13, RW, u32);
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register_bits!(icdipt_r13, target_55, u8, 24, 25);
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register_bits!(icdipt_r13, target_54, u8, 16, 17);
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register_bits!(icdipt_r13, target_53, u8, 8, 9);
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register_bits!(icdipt_r13, target_52, u8, 0, 1);
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register!(icdipt_r14, ICDIPTR14, RW, u32);
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register_bits!(icdipt_r14, target_59, u8, 24, 25);
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register_bits!(icdipt_r14, target_58, u8, 16, 17);
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register_bits!(icdipt_r14, target_57, u8, 8, 9);
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register_bits!(icdipt_r14, target_56, u8, 0, 1);
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register!(icdipt_r15, ICDIPTR15, RW, u32);
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register_bits!(icdipt_r15, target_63, u8, 24, 25);
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register_bits!(icdipt_r15, target_62, u8, 16, 17);
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register_bits!(icdipt_r15, target_61, u8, 8, 9);
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register_bits!(icdipt_r15, target_60, u8, 0, 1);
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register!(icdipt_r16, ICDIPTR16, RW, u32);
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register_bits!(icdipt_r16, target_67, u8, 24, 25);
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register_bits!(icdipt_r16, target_66, u8, 16, 17);
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register_bits!(icdipt_r16, target_65, u8, 8, 9);
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register_bits!(icdipt_r16, target_64, u8, 0, 1);
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register!(icdipt_r17, ICDIPTR17, RW, u32);
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register_bits!(icdipt_r17, target_71, u8, 24, 25);
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register_bits!(icdipt_r17, target_70, u8, 16, 17);
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register_bits!(icdipt_r17, target_69, u8, 8, 9);
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register_bits!(icdipt_r17, target_68, u8, 0, 1);
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register!(icdipt_r18, ICDIPTR18, RW, u32);
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register_bits!(icdipt_r18, target_75, u8, 24, 25);
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register_bits!(icdipt_r18, target_74, u8, 16, 17);
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register_bits!(icdipt_r18, target_73, u8, 8, 9);
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register_bits!(icdipt_r18, target_72, u8, 0, 1);
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register!(icdipt_r19, ICDIPTR19, RW, u32);
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register_bits!(icdipt_r19, target_79, u8, 24, 25);
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register_bits!(icdipt_r19, target_78, u8, 16, 17);
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register_bits!(icdipt_r19, target_77, u8, 8, 9);
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register_bits!(icdipt_r19, target_76, u8, 0, 1);
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register!(icdipt_r20, ICDIPTR20, RW, u32);
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register_bits!(icdipt_r20, target_83, u8, 24, 25);
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register_bits!(icdipt_r20, target_82, u8, 16, 17);
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register_bits!(icdipt_r20, target_81, u8, 8, 9);
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register_bits!(icdipt_r20, target_80, u8, 0, 1);
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register!(icdipt_r21, ICDIPTR21, RW, u32);
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register_bits!(icdipt_r21, target_87, u8, 24, 25);
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register_bits!(icdipt_r21, target_86, u8, 16, 17);
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register_bits!(icdipt_r21, target_85, u8, 8, 9);
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register_bits!(icdipt_r21, target_84, u8, 0, 1);
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register!(icdipt_r22, ICDIPTR22, RW, u32);
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register_bits!(icdipt_r22, target_91, u8, 24, 25);
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register_bits!(icdipt_r22, target_90, u8, 16, 17);
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register_bits!(icdipt_r22, target_89, u8, 8, 9);
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register_bits!(icdipt_r22, target_88, u8, 0, 1);
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register!(icdipt_r23, ICDIPTR23, RW, u32);
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register_bits!(icdipt_r23, target_95, u8, 24, 25);
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register_bits!(icdipt_r23, target_94, u8, 16, 17);
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register_bits!(icdipt_r23, target_93, u8, 8, 9);
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register_bits!(icdipt_r23, target_92, u8, 0, 1);
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register!(icdicf_r0, ICDICFR0, RO, u32);
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register_bits!(icdicf_r0, config_15, u8, 30, 31);
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register_bits!(icdicf_r0, config_14, u8, 28, 29);
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register_bits!(icdicf_r0, config_13, u8, 26, 27);
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register_bits!(icdicf_r0, config_12, u8, 24, 25);
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register_bits!(icdicf_r0, config_11, u8, 22, 23);
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|
||||||
register_bits!(icdicf_r0, config_10, u8, 20, 21);
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|
||||||
register_bits!(icdicf_r0, config_9, u8, 18, 19);
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|
||||||
register_bits!(icdicf_r0, config_8, u8, 16, 17);
|
|
||||||
register_bits!(icdicf_r0, config_7, u8, 14, 15);
|
|
||||||
register_bits!(icdicf_r0, config_6, u8, 12, 13);
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|
||||||
register_bits!(icdicf_r0, config_5, u8, 10, 11);
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|
||||||
register_bits!(icdicf_r0, config_4, u8, 8, 9);
|
|
||||||
register_bits!(icdicf_r0, config_3, u8, 6, 7);
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|
||||||
register_bits!(icdicf_r0, config_2, u8, 4, 5);
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|
||||||
register_bits!(icdicf_r0, config_1, u8, 2, 3);
|
|
||||||
register_bits!(icdicf_r0, config_0, u8, 0, 1);
|
|
||||||
|
|
||||||
register!(icdicf_r1, ICDICFR1, RW, u32);
|
|
||||||
register_bits!(icdicf_r1, config_31, u8, 30, 31);
|
|
||||||
register_bits!(icdicf_r1, config_30, u8, 28, 29);
|
|
||||||
register_bits!(icdicf_r1, config_29, u8, 26, 27);
|
|
||||||
register_bits!(icdicf_r1, config_28, u8, 24, 25);
|
|
||||||
register_bits!(icdicf_r1, config_27, u8, 22, 23);
|
|
||||||
|
|
||||||
register!(icdicf_r2, ICDICFR2, RW, u32);
|
|
||||||
register_bits!(icdicf_r2, config_47, u8, 30, 31);
|
|
||||||
register_bits!(icdicf_r2, config_46, u8, 28, 29);
|
|
||||||
register_bits!(icdicf_r2, config_45, u8, 26, 27);
|
|
||||||
register_bits!(icdicf_r2, config_44, u8, 24, 25);
|
|
||||||
register_bits!(icdicf_r2, config_43, u8, 22, 23);
|
|
||||||
register_bits!(icdicf_r2, config_42, u8, 20, 21);
|
|
||||||
register_bits!(icdicf_r2, config_41, u8, 18, 19);
|
|
||||||
register_bits!(icdicf_r2, config_40, u8, 16, 17);
|
|
||||||
register_bits!(icdicf_r2, config_39, u8, 14, 15);
|
|
||||||
register_bits!(icdicf_r2, config_38, u8, 12, 13);
|
|
||||||
register_bits!(icdicf_r2, config_37, u8, 10, 11);
|
|
||||||
register_bits!(icdicf_r2, config_36, u8, 8, 9);
|
|
||||||
register_bits!(icdicf_r2, config_35, u8, 6, 7);
|
|
||||||
register_bits!(icdicf_r2, config_34, u8, 4, 5);
|
|
||||||
register_bits!(icdicf_r2, config_33, u8, 2, 3);
|
|
||||||
register_bits!(icdicf_r2, config_32, u8, 0, 1);
|
|
||||||
|
|
||||||
register!(icdicf_r3, ICDICFR3, RW, u32);
|
|
||||||
register_bits!(icdicf_r3, config_63, u8, 30, 31);
|
|
||||||
register_bits!(icdicf_r3, config_62, u8, 28, 29);
|
|
||||||
register_bits!(icdicf_r3, config_61, u8, 26, 27);
|
|
||||||
register_bits!(icdicf_r3, config_60, u8, 24, 25);
|
|
||||||
register_bits!(icdicf_r3, config_59, u8, 22, 23);
|
|
||||||
register_bits!(icdicf_r3, config_58, u8, 20, 21);
|
|
||||||
register_bits!(icdicf_r3, config_57, u8, 18, 19);
|
|
||||||
register_bits!(icdicf_r3, config_56, u8, 16, 17);
|
|
||||||
register_bits!(icdicf_r3, config_55, u8, 14, 15);
|
|
||||||
register_bits!(icdicf_r3, config_54, u8, 12, 13);
|
|
||||||
register_bits!(icdicf_r3, config_53, u8, 10, 11);
|
|
||||||
register_bits!(icdicf_r3, config_52, u8, 8, 9);
|
|
||||||
register_bits!(icdicf_r3, config_51, u8, 6, 7);
|
|
||||||
register_bits!(icdicf_r3, config_50, u8, 4, 5);
|
|
||||||
register_bits!(icdicf_r3, config_49, u8, 2, 3);
|
|
||||||
register_bits!(icdicf_r3, config_48, u8, 0, 1);
|
|
||||||
|
|
||||||
register!(icdicf_r4, ICDICFR4, RW, u32);
|
|
||||||
register_bits!(icdicf_r4, config_79, u8, 30, 31);
|
|
||||||
register_bits!(icdicf_r4, config_78, u8, 28, 29);
|
|
||||||
register_bits!(icdicf_r4, config_77, u8, 26, 27);
|
|
||||||
register_bits!(icdicf_r4, config_76, u8, 24, 25);
|
|
||||||
register_bits!(icdicf_r4, config_75, u8, 22, 23);
|
|
||||||
register_bits!(icdicf_r4, config_74, u8, 20, 21);
|
|
||||||
register_bits!(icdicf_r4, config_73, u8, 18, 19);
|
|
||||||
register_bits!(icdicf_r4, config_72, u8, 16, 17);
|
|
||||||
register_bits!(icdicf_r4, config_71, u8, 14, 15);
|
|
||||||
register_bits!(icdicf_r4, config_70, u8, 12, 13);
|
|
||||||
register_bits!(icdicf_r4, config_69, u8, 10, 11);
|
|
||||||
register_bits!(icdicf_r4, config_68, u8, 8, 9);
|
|
||||||
register_bits!(icdicf_r4, config_67, u8, 6, 7);
|
|
||||||
register_bits!(icdicf_r4, config_66, u8, 4, 5);
|
|
||||||
register_bits!(icdicf_r4, config_65, u8, 2, 3);
|
|
||||||
register_bits!(icdicf_r4, config_64, u8, 0, 1);
|
|
||||||
|
|
||||||
register!(icdicf_r5, ICDICFR5, RW, u32);
|
|
||||||
register_bits!(icdicf_r5, config_95, u8, 30, 31);
|
|
||||||
register_bits!(icdicf_r5, config_94, u8, 28, 29);
|
|
||||||
register_bits!(icdicf_r5, config_93, u8, 26, 27);
|
|
||||||
register_bits!(icdicf_r5, config_92, u8, 24, 25);
|
|
||||||
register_bits!(icdicf_r5, config_91, u8, 22, 23);
|
|
||||||
register_bits!(icdicf_r5, config_90, u8, 20, 21);
|
|
||||||
register_bits!(icdicf_r5, config_89, u8, 18, 19);
|
|
||||||
register_bits!(icdicf_r5, config_88, u8, 16, 17);
|
|
||||||
register_bits!(icdicf_r5, config_87, u8, 14, 15);
|
|
||||||
register_bits!(icdicf_r5, config_86, u8, 12, 13);
|
|
||||||
register_bits!(icdicf_r5, config_85, u8, 10, 11);
|
|
||||||
register_bits!(icdicf_r5, config_84, u8, 8, 9);
|
|
||||||
register_bits!(icdicf_r5, config_83, u8, 6, 7);
|
|
||||||
register_bits!(icdicf_r5, config_82, u8, 4, 5);
|
|
||||||
register_bits!(icdicf_r5, config_81, u8, 2, 3);
|
|
||||||
register_bits!(icdicf_r5, config_80, u8, 0, 1);
|
|
||||||
|
|
||||||
register!(ppi_status, PpiStatus, RO, u32);
|
register!(ppi_status, PpiStatus, RO, u32);
|
||||||
register_bits!(ppi_status, ppi_status, u8, 11, 15);
|
register_bits!(ppi_status, ppi_status, u8, 11, 15);
|
||||||
register_bits!(ppi_status, sbz, u32, 0, 10);
|
register_bits!(ppi_status, sbz, u32, 0, 10);
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue