M-Labs/zynq-rs
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Add core0 interrupt return test

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This commit is contained in:
morgan 2023-11-14 15:01:37 +08:00
parent 40b3d2e057
commit 8d204cf0eb
1 changed files with 27 additions and 13 deletions
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40
experiments/src/main.rs
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@ -56,19 +56,29 @@ extern "C" {
static CORE1_RESTART: AtomicBool = AtomicBool::new(false); static CORE1_RESTART: AtomicBool = AtomicBool::new(false);
interrupt_handler!(IRQ, irq, __irq_stack0_start, __irq_stack1_start, { interrupt_handler!(IRQ, irq, __irq_stack0_start, __irq_stack1_start, {
if MPIDR.read().cpu_id() == 1{ let mpcore = mpcore::RegisterBlock::mpcore();
let mpcore = mpcore::RegisterBlock::mpcore(); let mut gic = gic::InterruptController::gic(mpcore);
let mut gic = gic::InterruptController::gic(mpcore); let id = gic.get_interrupt_id();
let id = gic.get_interrupt_id(); match MPIDR.read().cpu_id(){
if id.0 == 0 { 0 => {
gic.end_interrupt(id); if id.0 == 0 {
asm::exit_irq(); println!("Interrupting core0...");
SP.write(&mut __stack1_start as *mut _ as u32); gic.end_interrupt(id);
asm::enable_irq(); return;
CORE1_RESTART.store(false, Ordering::Relaxed); }
notify_spin_lock(); },
main_core1(); 1 => {
} if id.0 == 0 {
gic.end_interrupt(id);
asm::exit_irq();
SP.write(&mut __stack1_start as *mut _ as u32);
asm::enable_irq();
CORE1_RESTART.store(false, Ordering::Relaxed);
notify_spin_lock();
main_core1();
}
},
_ => {}
} }
stdio::drop_uart(); stdio::drop_uart();
println!("IRQ"); println!("IRQ");
@ -134,6 +144,10 @@ pub fn main_core0() {
ddr.memtest(); ddr.memtest();
ram::init_alloc_ddr(&mut ddr); ram::init_alloc_ddr(&mut ddr);
info!("Send software interrupt to core0");
interrupt_controller.send_sgi(gic::InterruptId(0), gic::CPUCore::Core0.into());
info!("Core0 returned from interrupt");
boot::Core1::start(false); boot::Core1::start(false);
let core1_req = unsafe { &mut CORE1_REQ.0 }; let core1_req = unsafe { &mut CORE1_REQ.0 };