From 85bd506132fe990a38bddc812b0de049c90d4d00 Mon Sep 17 00:00:00 2001 From: Astro Date: Sun, 27 Oct 2019 20:38:06 +0100 Subject: [PATCH] zynq::ddr: parameters --- src/main.rs | 2 +- src/zynq/clocks.rs | 47 +++++++++++++++++++++++---------------------- src/zynq/ddr/mod.rs | 14 ++++++++------ 3 files changed, 33 insertions(+), 30 deletions(-) diff --git a/src/main.rs b/src/main.rs index 49a4e6e..29914a2 100644 --- a/src/main.rs +++ b/src/main.rs @@ -87,7 +87,7 @@ const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef]; fn main() { println!("Main."); - zynq::clocks::CpuClocks::enable_ddr(1_066_000_000); + zynq::clocks::CpuClocks::enable_ddr(1_066_666_666); let pll_status = zynq::slcr::RegisterBlock::new().pll_status.read(); println!("PLLs: {}", pll_status); let clocks = zynq::clocks::CpuClocks::get(); diff --git a/src/zynq/clocks.rs b/src/zynq/clocks.rs index 83c5c34..45fda27 100644 --- a/src/zynq/clocks.rs +++ b/src/zynq/clocks.rs @@ -94,34 +94,35 @@ impl CpuClocks { /// 25.10.4 PLLs pub fn enable_ddr(target_clock: u32) { let fdiv = (target_clock / PS_CLK).min(66) as u16; - let regs = slcr::RegisterBlock::new(); - regs.ddr_pll_ctrl.modify(|_, w| w - .pll_pwrdwn(false) - .pll_bypass_force(true) - .pll_fdiv(fdiv) - ); let (pll_res, pll_cp, lock_cnt) = PLL_FDIV_LOCK_PARAM.iter() .filter(|(fdiv_max, _)| fdiv <= *fdiv_max) .nth(0) .expect("PLL_FDIV_LOCK_PARAM") .1.clone(); - regs.ddr_pll_cfg.write( - slcr::PllCfg::zeroed() - .pll_res(pll_res) - .pll_cp(pll_cp) - .lock_cnt(lock_cnt) - ); - regs.ddr_pll_ctrl.modify(|_, w| w - .pll_reset(true) - ); - regs.ddr_pll_ctrl.modify(|_, w| w - .pll_reset(false) - ); - while ! regs.pll_status.read().ddr_pll_lock() {} - regs.ddr_pll_ctrl.modify(|_, w| w - .pll_bypass_force(false) - .pll_bypass_qual(false) - ); + slcr::RegisterBlock::unlocked(|regs| { + regs.ddr_pll_ctrl.modify(|_, w| w + .pll_pwrdwn(false) + .pll_bypass_force(true) + .pll_fdiv(fdiv) + ); + regs.ddr_pll_cfg.write( + slcr::PllCfg::zeroed() + .pll_res(pll_res) + .pll_cp(pll_cp) + .lock_cnt(lock_cnt) + ); + regs.ddr_pll_ctrl.modify(|_, w| w + .pll_reset(true) + ); + regs.ddr_pll_ctrl.modify(|_, w| w + .pll_reset(false) + ); + while ! regs.pll_status.read().ddr_pll_lock() {} + regs.ddr_pll_ctrl.modify(|_, w| w + .pll_bypass_force(false) + .pll_bypass_qual(false) + ); + }); } } diff --git a/src/zynq/ddr/mod.rs b/src/zynq/ddr/mod.rs index 5cd83d9..45f5c51 100644 --- a/src/zynq/ddr/mod.rs +++ b/src/zynq/ddr/mod.rs @@ -36,7 +36,7 @@ impl DdrRam { /// Zynq-7000 AP SoC Technical Reference Manual: /// 10.6.1 DDR Clock Initialization fn clock_setup(clocks: &CpuClocks) { - CpuClocks::enable_ddr(1_066_000_000); + CpuClocks::enable_ddr(1_066_666_666); let ddr3x_clk_divisor = ((clocks.ddr - 1) / DDR_FREQ + 1).min(255) as u8; let ddr2x_clk_divisor = 3 * ddr3x_clk_divisor / 2; @@ -181,14 +181,16 @@ impl DdrRam { // TODO: move into trait pub fn ptr(&mut self) -> *mut u8 { - // 0x0010_0000 as *mut _ - 0x0020_0000 as *mut _ + 0x0010_0000 as *mut _ } pub fn size(&self) -> usize { - // #[cfg(feature = "target_zc706")] - // 1024 * 1024 * 1024 - 4 * 1024 * 1024 + #[cfg(feature = "target_zc706")] + let megabytes = 1024; + #[cfg(feature = "target_cora_z7_10")] + let megabytes = 512; + + megabytes * 1024 * 1024 } pub fn memtest(&mut self) {