From 78caca1f04291a05930d76c7b2f49bb262789e3c Mon Sep 17 00:00:00 2001 From: Astro Date: Thu, 28 Nov 2019 03:22:26 +0100 Subject: [PATCH] zynq::flash: setup additional signals --- src/zynq/flash/mod.rs | 48 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 47 insertions(+), 1 deletion(-) diff --git a/src/zynq/flash/mod.rs b/src/zynq/flash/mod.rs index 4fe09f7..cc1eadf 100644 --- a/src/zynq/flash/mod.rs +++ b/src/zynq/flash/mod.rs @@ -85,7 +85,53 @@ impl Flash<()> { .io_type(slcr::IoBufferType::Lvcmos18) ); - // TODO: optional 2nd chip setup + // Option: Add Second Device Chip Select + // 4. Configure MIO pin 0 for chip select 1 output. + slcr.mio_pin_00.write( + slcr::MioPin00::zeroed() + .l0_sel(true) + .io_type(slcr::IoBufferType::Lvcmos18) + .pullup(true) + ); + + // Option: Add Second Serial Clock + // 5. Configure MIO pin 9 for serial clock 1 output. + slcr.mio_pin_09.write( + slcr::MioPin09::zeroed() + .l0_sel(true) + .io_type(slcr::IoBufferType::Lvcmos18) + ); + + // Option: Add 4-bit Data + // 6. Configure MIO pins 10 through 13 for I/O. + slcr.mio_pin_10.write( + slcr::MioPin10::zeroed() + .l0_sel(true) + .io_type(slcr::IoBufferType::Lvcmos18) + ); + slcr.mio_pin_11.write( + slcr::MioPin11::zeroed() + .l0_sel(true) + .io_type(slcr::IoBufferType::Lvcmos18) + ); + slcr.mio_pin_12.write( + slcr::MioPin12::zeroed() + .l0_sel(true) + .io_type(slcr::IoBufferType::Lvcmos18) + ); + slcr.mio_pin_13.write( + slcr::MioPin13::zeroed() + .l0_sel(true) + .io_type(slcr::IoBufferType::Lvcmos18) + ); + + // Option: Add Feedback Output Clock + // 7. Configure MIO pin 8 for feedback clock. + slcr.mio_pin_08.write( + slcr::MioPin08::zeroed() + .l0_sel(true) + .io_type(slcr::IoBufferType::Lvcmos18) + ); }); }