From 6af453494bcc745f1934966b7423088d27e1f36b Mon Sep 17 00:00:00 2001 From: pca006132 Date: Sat, 26 Sep 2020 16:28:08 +0800 Subject: [PATCH] libboard_zynq/ddr: use ps7_init for redpitaya ddr --- libboard_zynq/src/ddr/mod.rs | 29 +++++-- libboard_zynq/src/ps7_init/mod.rs | 4 +- libboard_zynq/src/ps7_init/redpitaya.rs | 106 ++++++++++++++++++++++++ 3 files changed, 129 insertions(+), 10 deletions(-) create mode 100644 libboard_zynq/src/ps7_init/redpitaya.rs diff --git a/libboard_zynq/src/ddr/mod.rs b/libboard_zynq/src/ddr/mod.rs index 7d8019e..c351b9f 100644 --- a/libboard_zynq/src/ddr/mod.rs +++ b/libboard_zynq/src/ddr/mod.rs @@ -4,6 +4,9 @@ use crate::{print, println}; use super::slcr::{self, DdriobVrefSel}; use super::clocks::{Clocks, source::{DdrPll, ClockSource}}; +#[cfg(feature = "target_redpitaya")] +use super::ps7_init; + mod regs; #[cfg(feature = "target_zc706")] @@ -27,15 +30,23 @@ pub struct DdrRam { impl DdrRam { pub fn ddrram() -> Self { - let clocks = Self::clock_setup(); - Self::calibrate_iob_impedance(&clocks); - Self::configure_iob(); - - let regs = regs::RegisterBlock::ddrc(); - let mut ddr = DdrRam { regs }; - ddr.configure(); - ddr.reset_ddrc(); - ddr + if cfg!(feature = "target_redpitaya") { + // We have not yet fixed red pitaya initialization yet. It seems + // that the clock configuration, iob settings and ddr settings are + // all problematic + ps7_init::apply(); + let regs = regs::RegisterBlock::ddrc(); + DdrRam { regs } + } else { + let clocks = Self::clock_setup(); + Self::calibrate_iob_impedance(&clocks); + Self::configure_iob(); + let regs = regs::RegisterBlock::ddrc(); + let mut ddr = DdrRam { regs }; + ddr.configure(); + ddr.reset_ddrc(); + ddr + } } /// Zynq-7000 AP SoC Technical Reference Manual: diff --git a/libboard_zynq/src/ps7_init/mod.rs b/libboard_zynq/src/ps7_init/mod.rs index 1d5373b..1d9a5f4 100644 --- a/libboard_zynq/src/ps7_init/mod.rs +++ b/libboard_zynq/src/ps7_init/mod.rs @@ -1,12 +1,14 @@ -#![cfg(feature = "target_zc706")] use crate::println; mod zc706; +mod redpitaya; // mod cora_z7_10; #[cfg(feature = "target_zc706")] use zc706 as target; +#[cfg(feature = "target_redpitaya")] +use redpitaya as target; // #[cfg(feature = "target_cora_z7_10")] // use cora_z7_10 as target; diff --git a/libboard_zynq/src/ps7_init/redpitaya.rs b/libboard_zynq/src/ps7_init/redpitaya.rs new file mode 100644 index 0000000..cf6ab97 --- /dev/null +++ b/libboard_zynq/src/ps7_init/redpitaya.rs @@ -0,0 +1,106 @@ +use super::InitOp::{self, *}; + +pub const INIT_DATA: &'static [InitOp] = &[ + MaskWrite(0xF8000008, 0xFFFFFFFF, 0x0000DF0D), + MaskWrite(0xF8000124, 0xFFF00003 ,0x0C200003), + MaskWrite(0xF8000B40, 0x00000FFF, 0x00000600), + MaskWrite(0xF8000B44, 0x00000FFF, 0x00000600), + MaskWrite(0xF8000B48, 0x00000FFF, 0x00000672), + MaskWrite(0xF8000B4C, 0x00000FFF, 0x00000800), + MaskWrite(0xF8000B50, 0x00000FFF, 0x00000674), + MaskWrite(0xF8000B54, 0x00000FFF, 0x00000800), + MaskWrite(0xF8000B58, 0x00000FFF, 0x00000600), + MaskWrite(0xF8000B5C, 0xFFFFFFFF, 0x0018C61C), + MaskWrite(0xF8000B60, 0xFFFFFFFF, 0x00F9861C), + MaskWrite(0xF8000B64, 0xFFFFFFFF, 0x00F9861C), + MaskWrite(0xF8000B68, 0xFFFFFFFF, 0x00F9861C), + MaskWrite(0xF8000B6C, 0x00007FFF, 0x00000220), + MaskWrite(0xF8000B70, 0x00000001, 0x00000001), + MaskWrite(0xF8000B70, 0x00000021, 0x00000020), + MaskWrite(0xF8000B70, 0x07FEFFFF, 0x00000823), + MaskWrite(0xF8000700, 0x00003FFF, 0x00001600), + MaskWrite(0xF8000704, 0x00003FFF, 0x00001602), + MaskWrite(0xF8000004, 0xFFFFFFFF, 0x0000767B), + MaskWrite(0xF8006000, 0x0001FFFF, 0x00000084), + MaskWrite(0xF8006004, 0x0007FFFF, 0x00001081), + MaskWrite(0xF8006008, 0x03FFFFFF, 0x03C0780F), + MaskWrite(0xF800600C, 0x03FFFFFF, 0x02001001), + MaskWrite(0xF8006010, 0x03FFFFFF, 0x00014001), + MaskWrite(0xF8006014, 0x001FFFFF, 0x0004281B), + MaskWrite(0xF8006018, 0xF7FFFFFF, 0x44E458D2), + MaskWrite(0xF800601C, 0xFFFFFFFF, 0x720238E5), + MaskWrite(0xF8006020, 0x7FDFFFFC, 0x270872D0), + MaskWrite(0xF8006024, 0x0FFFFFC3, 0x00000000), + MaskWrite(0xF8006028, 0x00003FFF, 0x00002007), + MaskWrite(0xF800602C, 0xFFFFFFFF, 0x00000008), + MaskWrite(0xF8006030, 0xFFFFFFFF, 0x00040930), + MaskWrite(0xF8006034, 0x13FF3FFF, 0x000116D4), + MaskWrite(0xF8006038, 0x00000003, 0x00000000), + MaskWrite(0xF800603C, 0x000FFFFF, 0x00000666), + MaskWrite(0xF8006040, 0xFFFFFFFF, 0xFFFF0000), + MaskWrite(0xF8006044, 0x0FFFFFFF, 0x0F555555), + MaskWrite(0xF8006048, 0x0003F03F, 0x0003C008), + MaskWrite(0xF8006050, 0xFF0F8FFF, 0x77010800), + MaskWrite(0xF8006058, 0x00010000, 0x00000000), + MaskWrite(0xF800605C, 0x0000FFFF, 0x00005003), + MaskWrite(0xF8006060, 0x000017FF, 0x0000003E), + MaskWrite(0xF8006064, 0x00021FE0, 0x00020000), + MaskWrite(0xF8006068, 0x03FFFFFF, 0x00284141), + MaskWrite(0xF800606C, 0x0000FFFF, 0x00001610), + MaskWrite(0xF8006078, 0x03FFFFFF, 0x00466111), + MaskWrite(0xF800607C, 0x000FFFFF, 0x00032222), + MaskWrite(0xF80060A4, 0xFFFFFFFF, 0x10200802), + MaskWrite(0xF80060A8, 0x0FFFFFFF, 0x0690CB73), + MaskWrite(0xF80060AC, 0x000001FF, 0x000001FE), + MaskWrite(0xF80060B0, 0x1FFFFFFF, 0x1CFFFFFF), + MaskWrite(0xF80060B4, 0x00000200, 0x00000200), + MaskWrite(0xF80060B8, 0x01FFFFFF, 0x00200066), + MaskWrite(0xF80060C4, 0x00000003, 0x00000000), + MaskWrite(0xF80060C8, 0x000000FF, 0x00000000), + MaskWrite(0xF80060DC, 0x00000001, 0x00000000), + MaskWrite(0xF80060F0, 0x0000FFFF, 0x00000000), + MaskWrite(0xF80060F4, 0x0000000F, 0x00000008), + MaskWrite(0xF8006114, 0x000000FF, 0x00000000), + MaskWrite(0xF8006118, 0x7FFFFFCF, 0x40000001), + MaskWrite(0xF800611C, 0x7FFFFFCF, 0x40000001), + MaskWrite(0xF8006120, 0x7FFFFFCF, 0x40000000), + MaskWrite(0xF8006124, 0x7FFFFFCF, 0x40000000), + MaskWrite(0xF800612C, 0x000FFFFF, 0x00029000), + MaskWrite(0xF8006130, 0x000FFFFF, 0x00029000), + MaskWrite(0xF8006134, 0x000FFFFF, 0x00029000), + MaskWrite(0xF8006138, 0x000FFFFF, 0x00029000), + MaskWrite(0xF8006140, 0x000FFFFF, 0x00000035), + MaskWrite(0xF8006144, 0x000FFFFF, 0x00000035), + MaskWrite(0xF8006148, 0x000FFFFF, 0x00000035), + MaskWrite(0xF800614C, 0x000FFFFF, 0x00000035), + MaskWrite(0xF8006154, 0x000FFFFF, 0x00000080), + MaskWrite(0xF8006158, 0x000FFFFF, 0x00000080), + MaskWrite(0xF800615C, 0x000FFFFF, 0x00000080), + MaskWrite(0xF8006160, 0x000FFFFF, 0x00000080), + MaskWrite(0xF8006168, 0x001FFFFF, 0x000000F9), + MaskWrite(0xF800616C, 0x001FFFFF, 0x000000F9), + MaskWrite(0xF8006170, 0x001FFFFF, 0x000000F9), + MaskWrite(0xF8006174, 0x001FFFFF, 0x000000F9), + MaskWrite(0xF800617C, 0x000FFFFF, 0x000000C0), + MaskWrite(0xF8006180, 0x000FFFFF, 0x000000C0), + MaskWrite(0xF8006184, 0x000FFFFF, 0x000000C0), + MaskWrite(0xF8006188, 0x000FFFFF, 0x000000C0), + MaskWrite(0xF8006190, 0x6FFFFEFE, 0x00040080), + MaskWrite(0xF8006194, 0x000FFFFF, 0x0001FC82), + MaskWrite(0xF8006204, 0xFFFFFFFF, 0x00000000), + MaskWrite(0xF8006208, 0x000703FF, 0x000003FF), + MaskWrite(0xF800620C, 0x000703FF, 0x000003FF), + MaskWrite(0xF8006210, 0x000703FF, 0x000003FF), + MaskWrite(0xF8006214, 0x000703FF, 0x000003FF), + MaskWrite(0xF8006218, 0x000F03FF, 0x000003FF), + MaskWrite(0xF800621C, 0x000F03FF, 0x000003FF), + MaskWrite(0xF8006220, 0x000F03FF, 0x000003FF), + MaskWrite(0xF8006224, 0x000F03FF, 0x000003FF), + MaskWrite(0xF80062A8, 0x00000FF5, 0x00000000), + MaskWrite(0xF80062AC, 0xFFFFFFFF, 0x00000000), + MaskWrite(0xF80062B0, 0x003FFFFF, 0x00005125), + MaskWrite(0xF80062B4, 0x0003FFFF, 0x000012A8), + MaskPoll(0xF8000B74, 0x00002000), + MaskWrite(0xF8006000, 0x0001FFFF, 0x00000085), + MaskPoll(0xF8006054, 0x00000007), +];