From 51c39f032e5f6326001d62b509abf1aff4e6ae16 Mon Sep 17 00:00:00 2001 From: Astro Date: Sat, 25 May 2019 02:38:05 +0200 Subject: [PATCH] run with the cora z7-10 --- Cargo.toml | 5 +++++ README.md | 23 +++++++++++++++++++-- cora-z7-10.cfg | 49 ++++++++++++++++++++++++++++++++++++++++++++ src/main.rs | 2 +- src/uart/mod.rs | 54 ++++++++++++++++++++++++++++++++++++++++++++----- 5 files changed, 125 insertions(+), 8 deletions(-) create mode 100644 cora-z7-10.cfg diff --git a/Cargo.toml b/Cargo.toml index d89204d..27c6d03 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -12,6 +12,11 @@ lto = false panic = "abort" debug = true +[features] +target_zc706 = [] +target_cora_z7_10 = [] +default = ["target_zc706"] + [dependencies] panic-abort = "0.3" r0 = "0.2" diff --git a/README.md b/README.md index 468149e..a3232ca 100644 --- a/README.md +++ b/README.md @@ -1,7 +1,15 @@ -# Debugging +# Build + +```shell +nix-shell --command "cargo build --release" +``` + +# Debug ## Using the Xilinx toolchain +Tested with the ZC706 board. + Run the Xilinx Microprocessor Debugger: ```shell /opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64/xmd @@ -26,5 +34,16 @@ target remote :1234 Proceed using gdb with `load`, `c` -## Using OpenOCD: not working +## Using OpenOCD +### Resources for the ZC706 + +https://devel.rtems.org/wiki/Debugging/OpenOCD/Xilinx_Zynq +https://github.com/nathanrossi/meta-random/tree/master/openocd-zynq + +### Running on the Cora Z7-10 + +```shell +nix-shell --command "cargo build --release --no-default-features --features=target_cora_z7_10" +openocd -f cora-z7-10.cfg +``` diff --git a/cora-z7-10.cfg b/cora-z7-10.cfg new file mode 100644 index 0000000..621d9ea --- /dev/null +++ b/cora-z7-10.cfg @@ -0,0 +1,49 @@ +source [find interface/ftdi/digilent-hs1.cfg] +source [find target/zynq_7000.cfg] + +set _TARGETNAME_0 "zynq.cpu0" +set _TARGETNAME_1 "zynq.cpu1" +set _SMP 1 + +proc zynq_restart { wait } { + global _SMP + global _TARGETNAME_0 + global _TARGETNAME_1 + set target0 $_TARGETNAME_0 + set target1 $_TARGETNAME_1 + echo "Zynq reset, resetting the board ... " + poll off + # + # Issue the reset via the SLCR + # + catch { + mww phys 0xF8000008 0xDF0D + mww phys 0xF8000200 1 + } + echo "Zynq reset waiting for $wait msecs ... " + sleep $wait + # + # Reconnect the DAP etc due to the reset. + # + $target0 cortex_a dbginit + $target0 arm core_state arm + if { $_SMP } { + $target1 arm core_state arm + $target1 cortex_a dbginit + cortex_a smp_off + } + poll on + # + # We can now halt the core. + # + if { $_SMP } { + targets $target1 + halt + } + targets $target0 + halt + #zynq_rtems_setup +} + +init +zynq_restart 100 diff --git a/src/main.rs b/src/main.rs index 7339ccb..b16e8c3 100644 --- a/src/main.rs +++ b/src/main.rs @@ -72,7 +72,7 @@ fn l1_cache_init() { } fn main() { - let mut uart = Uart::uart1(115_200); + let mut uart = Uart::serial(115_200); loop { for i in 0.. { writeln!(uart, "i={}\r", i); diff --git a/src/uart/mod.rs b/src/uart/mod.rs index 7808ce0..80ea0e5 100644 --- a/src/uart/mod.rs +++ b/src/uart/mod.rs @@ -9,23 +9,25 @@ mod baud_rate_gen; /// Determined through experimentation. Actually supposed to be /// 1 GHz (IO PLL) / 0x14 (slcr.UART_CLK_CTRL[DIVISOR]) = 50 MHz. +#[cfg(feature = "target_zc706")] const UART_REF_CLK: u32 = 45_000_000; +#[cfg(feature = "target_cora_z7_10")] +const UART_REF_CLK: u32 = 66_000_000; pub struct Uart { regs: &'static mut regs::RegisterBlock, } impl Uart { - pub fn uart1(baudrate: u32) -> Self { + #[cfg(feature = "target_zc706")] + pub fn serial(baudrate: u32) -> Self { slcr::RegisterBlock::unlocked(|slcr| { - slcr.uart_rst_ctrl.reset_uart1(); - // Route UART 1 RxD/TxD Signals to MIO Pins // TX pin slcr.mio_pin_48.write( slcr::MioPin48::zeroed() .l3_sel(0b111) - .io_type(0b001) + .io_type(slcr::IoBufferType::Lvcmos18) .pullup(true) ); // RX pin @@ -33,10 +35,52 @@ impl Uart { slcr::MioPin49::zeroed() .tri_enable(true) .l3_sel(0b111) - .io_type(0b001) + .io_type(slcr::IoBufferType::Lvcmos18) .pullup(true) ); + }); + Self::uart1(baudrate) + } + #[cfg(feature = "target_cora_z7_10")] + pub fn serial(baudrate: u32) -> Self { + slcr::RegisterBlock::unlocked(|slcr| { + // Route UART 0 RxD/TxD Signals to MIO Pins + // TX pin + slcr.mio_pin_15.write( + slcr::MioPin15::zeroed() + .l3_sel(0b111) + .io_type(slcr::IoBufferType::Lvcmos33) + .pullup(true) + ); + // RX pin + slcr.mio_pin_14.write( + slcr::MioPin14::zeroed() + .tri_enable(true) + .l3_sel(0b111) + .io_type(slcr::IoBufferType::Lvcmos33) + .pullup(true) + ); + }); + Self::uart0(baudrate) + } + + pub fn uart0(baudrate: u32) -> Self { + slcr::RegisterBlock::unlocked(|slcr| { + slcr.uart_rst_ctrl.reset_uart0(); + slcr.aper_clk_ctrl.enable_uart0(); + slcr.uart_clk_ctrl.enable_uart0(); + }); + let mut self_ = Uart { + regs: regs::RegisterBlock::uart0(), + }; + self_.configure(baudrate); + self_ + } + + pub fn uart1(baudrate: u32) -> Self { + slcr::RegisterBlock::unlocked(|slcr| { + slcr.uart_rst_ctrl.reset_uart1(); slcr.aper_clk_ctrl.enable_uart1(); slcr.uart_clk_ctrl.enable_uart1(); });