libcortex_r5: add register definitions
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use libregister::{
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register_bit, register_bits,
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RegisterR, RegisterW, RegisterRW,
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};
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use libcortex_a9::{def_reg_r, def_reg_w, wrap_reg};
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pub use libcortex_a9::regs::{SP, LR};
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/// Multiprocessor Affinity Register
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pub struct MPIDR;
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wrap_reg!(mpidr);
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def_reg_r!(MPIDR, mpidr::Read, "mrc p15, 0, $0, c0, c0, 5");
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// CPU ID
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register_bits!(mpidr, cpu_id, u8, 0, 7);
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// group ID
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register_bits!(mpidr, group_id, u8, 8, 15);
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// 0b11 if part of uniprocessor system
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register_bits!(mpidr, u, u8, 30, 31);
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/// System Control Register
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pub struct SCTLR;
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wrap_reg!(sctlr);
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def_reg_r!(SCTLR, sctlr::Read, "mrc p15, 0, $0, c1, c0, 0");
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def_reg_w!(SCTLR, sctlr::Write, "mrc p15, 0, $0, c1, c0, 0");
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// MPU enable
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register_bit!(sctlr, m, 0);
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// strict alignment
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register_bit!(sctlr, a, 1);
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// L1 data cache enable
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register_bit!(sctlr, c, 2);
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// enable SWP and SWPB instructions
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register_bit!(sctlr, sw, 10);
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// enable branch prediction (SBO)
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register_bit!(sctlr, z, 11);
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// L1 instruction cache enable
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register_bit!(sctlr, i, 12);
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// Determines the location of exception vectors:
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// 0 = normal exception vectors selected, address range = 0x00000000-0x0000001C
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// 1 = high exception vectors (HIVECS) selected, address range = 0xFFFF0000-0xFFFF001C.
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// The primary input VINITHIm defines the reset value.
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register_bit!(sctlr, v, 13);
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// Round-robin bit, controls replacement strategy for instruction and data caches:
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// 0 = random replacement strategy
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// 1 = round-robin replacement strategy.
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// The reset value of this bit is 0. The processor always uses a random replacement strategy, regardless of the state
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// of this bit.
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register_bit!(sctlr, rr, 14);
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// MPU background region enable
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register_bit!(sctlr, br, 17);
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// Divide by zero:
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// 0 = do not generate an Undefined Instruction exception
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// 1 = generate an Undefined Instruction exception.
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// The reset value of this bit is 0
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register_bit!(sctlr, dz, 19);
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// Fast Interrupts enable.
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// On the processor Fast Interrupts are always enabled. This bit is SBO
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register_bit!(sctlr, fi, 21);
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// Configures vectored interrupt:
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// 0 = exception vector address for IRQ is 0x00000018 or 0xFFFF0018. See V bit.
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// 1 = VIC controller provides handler address for IRQ.
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// The reset value of this bit is 0.
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register_bit!(sctlr, ve, 24);
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// Determines how the E bit in the CPSR is set on an exception:
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// 0 = CPSR E bit is set to 0 on an exception
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// 1 = CPSR E bit is set to 1 on an exception.
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// The primary input CFGEE defines the reset value.
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register_bit!(sctlr, ee, 25);
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// NMFI, non-maskable fast interrupt enable:
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// 0 = Software can disable FIQs
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// 1 = Software cannot disable FIQs.
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// This bit is read-only. The configuration input CFGNMFIm defines its value.
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register_bit!(sctlr, nmfi, 27);
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// TEX Remap Enable. On the processor this bit is SBZ.
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register_bit!(sctlr, tre, 28);
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// Access Flag Enable. On the processor this bit is SBZ.
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register_bit!(sctlr, afe, 29);
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// Thumb exception enable:
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// 0 = enable ARM exception generation
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// 1 = enable Thumb exception generation.
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// The primary input TEINIT defines the reset value
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register_bit!(sctlr, te, 30);
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// Identifies little or big instruction endianness in use:
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// 0 = little-endianness
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// 1 = big-endianness.
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// The primary input CFGIE defines the value. This bit is read-only
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register_bit!(sctlr, ie, 31);
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/// Auxiliary Control Register
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pub struct ACTLR;
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wrap_reg!(actlr);
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def_reg_r!(ACTLR, actlr::Read, "mrc p15, 0, $0, c1, c0, 1");
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def_reg_w!(ACTLR, actlr::Write, "mcr p15, 0, $0, c1, c0, 1");
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// A(B0/1)TCM external error enable:
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// 0 = Disabled
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// 1 = Enabled.
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// The primary input ERRENRAMm[0] defines the reset value.
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register_bit!(actlr, atcmecen, 0);
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register_bit!(actlr, b0tcmecen, 1);
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register_bit!(actlr, b1tcmecen, 2);
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// Cache error control for cache parity and ECC errors
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register_bits!(actlr, cec, u8, 3, 5);
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// Disable low interrupt latency on all load/store instructions
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register_bit!(actlr, dils, 6);
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// sMOV of a divide does not complete out of order.
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// No other instruction is issued until the divide is finished
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register_bit!(actlr, smov, 7);
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// Force D-side to not-shared when MPU is off:
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// 0 = Normal operation. This is the reset value.
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// 1 = D-side normal Non-cacheable forced to Non-shared when MPU is off.
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register_bit!(actlr, fdsns, 8);
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// Force write-through (WT) for write-back (WB) regions:
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// 0 = No forcing of WT. This is the reset value.
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// 1 = WT forced for WB regions
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register_bit!(actlr, fwt, 9);
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// Force outer read allocate (ORA) for outer write allocate (OWA) regions:
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// 0 = No forcing of ORA. This is the reset value.
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// 1 = ORA forced for OWA regions
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register_bit!(actlr, fora, 10);
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// Disable data forwarding for Non-cacheable accesses in the AXI master:
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// 0 = Normal operation. This is the reset value.
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// 1 = Disable data forwarding for Non-cacheable accesses
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register_bit!(actlr, dnch, 11);
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// Enable random parity error generation:
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// 0 = Random parity error generation disabled. This is the reset value.
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// 1 = Enable random parity error generation in the cache RAMs.
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register_bit!(actlr, erpeg, 12);
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// Disable linefill optimization in the AXI master:
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// 0 = Normal operation. This is the reset value.
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// 1 = Limits the number of outstanding data linefills to two
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register_bit!(actlr, dlfo, 13);
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// Disable write burst in the AXI master:
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// 0 = Normal operation. This is the reset value.
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// 1 = Disable write burst optimization
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register_bit!(actlr, dbwr, 14);
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// This field controls the branch prediction policy:
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// b00 = Normal operation. This is the reset value.
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// b01 = Branch always taken and history table updates disabled.
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// b10 = Branch always not taken and history table updates disabled.
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// b11 = Reserved. Behavior is Unpredictable if this field is set to b11
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register_bits!(actlr, bp, u8, 15, 16);
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// Return stack disable:
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// 0 = Normal return stack operation. This is the reset value.
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// 1 = Return stack disabled.
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register_bit!(actlr, rsdis, 17);
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// Fetch rate control disable:
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// 0 = Normal fetch rate control operation. This is the reset value.
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// 1 = Fetch rate control disabled.
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register_bit!(actlr, frcdis, 19);
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// Disable Branch History (BH) extension:
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// 0 = Enable the extension. This is the reset value.
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// 1 = Disable the extension
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register_bit!(actlr, dbhe, 20);
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// Disable end of loop prediction:
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// 0 = Enable loop prediction. This is the reset value.
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// 1 = Disable loop prediction.
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register_bit!(actlr, deolp, 21);
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// Disable Low Interrupt Latency (LIL) on load/store multiples:
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// 0 = Enable LIL on load/store multiples. This is the reset value.
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// 1 = Disable LIL on all load/store multiples.
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register_bit!(actlr, dilsm, 22);
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// AXI slave cache RAM non-privileged access enable:
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// 0 = Disabled. This is the reset value.
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// 1 = Enabled
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register_bit!(actlr, axiscuen, 23);
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// AXI slave cache RAM access enable:
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// 0 = Disabled. This is the reset value.
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// 1 = Enabled
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register_bit!(actlr, axiscen, 24);
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// A(B0/1)TCM ECC check enable:
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// 0 = Disabled
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// 1 = Enabled
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// The primary input PARECCENRAMm[0] defines the reset value
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register_bit!(actlr, atcmpcen, 25);
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register_bit!(actlr, b0tcmpcen, 26);
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register_bit!(actlr, b1tcmpcen, 27);
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// Case A(B1, B2, C) dual issue control:
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// 0 = Enabled. This is the reset value.
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// 1 = Disabled.
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register_bit!(actlr, diadi, 28);
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register_bit!(actlr, dib1di, 29);
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register_bit!(actlr, dib2di, 30);
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register_bit!(actlr, dicdi, 31);
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/// Secondary Auxiliary Control Register
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pub struct SACTLR;
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wrap_reg!(sactlr);
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def_reg_r!(SACTLR, sactlr::Read, "mrc p15, 0, $0, c15, c0, 0");
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def_reg_w!(SACTLR, sactlr::Write, "mcr p15, 0, $0, c15, c0, 0");
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// Enables 64-bit stores for the ATCM. When enabled, the processor uses read-modify-write to ensure that all
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// reads and writes presented on the ATCM port are 64 bits wide.
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// 0 = Disabled
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// 1 = Enabled.
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// The primary input RMWENRAMm[0] defines the reset value.
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register_bit!(sactlr, atcmrmw, 0);
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register_bit!(sactlr, btcmrmw, 1);
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// Correction for internal ECC logic on ATCM port.
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// 0 = Enabled. This is the reset value.
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// 1 = Disabled
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register_bit!(sactlr, atcmecc, 2);
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register_bit!(sactlr, btcmecc, 3);
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// Floating-point input denormal exception output mask.
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// 0 = Mask floating-point input denormal exception output. The output FPIDCm is forced to zero. This is
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// the reset value.
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// 1 = Propagate floating-point input denormal exception flag FPSCR.IDC to output FPIDCm
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register_bit!(sactlr, idc, 8);
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// Floating-point divide-by-zero exception output mask.
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// 0 = Mask floating-point divide-by-zero exception output. The output FPDZCm is forced to zero. This is
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// the reset value.
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// 1 = Propagate floating-point divide-by-zero exception flag FPSCR.DZC to output FPDZCm
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register_bit!(sactlr, dzc, 9);
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// Floating-point invalid operation exception output mask.
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// 0 = Mask floating-point invalid operation exception output. The output FPIOCm is forced to zero. This is
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// the reset value.
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// 1 = Propagate floating-point invalid operation exception flag FPSCR.IOC to output FPIOCm.
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register_bit!(sactlr, ioc, 10);
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// Floating-point underflow exception output mask.
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// 0 = Mask floating-point underflow exception output. The output FPUFCm is forced to zero. This is the
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// reset value.
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// 1 = Propagate floating-point underflow exception flag FPSCR.UFC to output FPUFCm
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register_bit!(sactlr, ufc, 11);
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// Floating-point overflow exception output mask.
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// 0 = Mask floating-point overflow exception output. The output FPOFCm is forced to zero. This is the reset
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// value.
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// 1 = Propagate floating-point overflow exception flag FPSCR.OFC to output FPOFCm
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register_bit!(sactlr, ofc, 12);
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// Floating-point inexact exception output mask.
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// 0 = Mask floating-point inexact exception output. The output FPIXCm is forced to zero. This is the reset
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// value.
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// 1 = Propagate floating point inexact exception flag FPSCR.IXC to output FPIXCm
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register_bit!(sactlr, ixc, 13);
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// Out-of-order FMACS control.
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// 0 = Enabled. This is the reset value.
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// 1 = Disabled
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register_bit!(sactlr, doofmacs, 16);
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// Out-of-order double-precision floating point instruction control.
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// 0 = Enabled. This is the reset value.
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// 1 = Disabled.
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register_bit!(sactlr, doodpfp, 17);
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// F1/F3/F4dual issue control.
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// 0 = Enabled. This is the reset value.
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// 1 = Disabled.
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register_bit!(sactlr, ddi, 18);
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// F2_Id/F2_st/F2D dual issue control.
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// 0 = Enabled. This is the reset value.
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// 1 = Disabled
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register_bit!(sactlr, df2di, 19);
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// F6 dual issue control.
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// 0 = Enabled. This is the reset value.
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// 1 = Disabled
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register_bit!(sactlr, df6di, 20);
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// Enable random 2-bit error generation in cache RAMs. This bit has no effect unless ECC is configured, see
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// Configurable options on page 1-6.
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// 0 = Disabled. This is the reset value.
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// 1 = Enabled.
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register_bit!(sactlr, dr2b, 21);
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// Disable hard-error support in the caches.
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// 0 = Enabled. The cache logic recovers from some hard errors.
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// 1 = Disabled. Most hard errors in the caches are fatal. This is the reset value
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register_bit!(sactlr, dche, 22);
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/// Data Fault Status Register
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pub struct DFSR;
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wrap_reg!(dfsr);
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def_reg_r!(DFSR, dfsr::Read, "mrc p15, 0, $0, c5, c0, 0");
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// Indicates the type of fault generated. To determine the data fault, you must use bit [12] and bit [10] in
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// conjunction with bits [3:0].
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register_bits!(dfsr, status, u8, 0, 3);
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register_bit!(dfsr, s, 10);
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// Indicates whether a read or write access caused an abort:
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// 0 = read access caused the abort
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// 1 = write access caused the abort.
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register_bit!(dfsr, rw, 11);
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// Distinguishes between an AXI Decode or Slave error on an external abort. This bit is only valid for external
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// aborts. For all other aborts types of abort, this bit is set to zero:
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// 0 = AXI Decode error (DECERR), or AHB error, caused the abort
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// 1 = AXI Slave error (SLVERR), or unsupported exclusive access, for example exclusive access using the AHB
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// peripheral port, caused the abort.
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register_bit!(dfsr, sd, 12);
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/// Data Fault Address Register
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pub struct DFAR;
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def_reg_r!(DFAR, u32, "mrc p15, 0, $0, c6, c0, 0");
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/// MPU Type Register
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pub struct MPUIR;
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wrap_reg!(mpuir);
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def_reg_r!(MPUIR, mpuir::Read, "mrc p15, 0, $0, c0, c0, 4");
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// number of unified MPU regions (0, 12, or 16)
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register_bits!(mpuir, d_region, u8, 8, 15);
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/// MPU Region Number Register
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pub struct RGNR;
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wrap_reg!(rgnr);
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def_reg_r!(RGNR, rgnr::Read, "mrc p15, 0, $0, c6, c2, 0");
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def_reg_w!(RGNR, rgnr::Write, "mcr p15, 0, $0, c6, c2, 0");
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register_bits!(rgnr, region, u8, 0, 3);
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/// MPU Region Access Control Registers
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pub struct RACTLR;
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wrap_reg!(ractlr);
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def_reg_r!(RACTLR, ractlr::Read, "mrc p15, 0, $0, c6, c1, 4");
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def_reg_w!(RACTLR, ractlr::Write, "mcr p15, 0, $0, c6, c1, 4");
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// bufferable
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register_bit!(ractlr, b, 0);
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// cacheable
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register_bit!(ractlr, c, 1);
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// shareable
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register_bit!(ractlr, s, 2);
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// type extension
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register_bits!(ractlr, tex, u8, 3, 5);
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// Access permission
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register_bits!(ractlr, ap, u8, 8, 10);
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// Execute Never. Determines if a region of memory is executable:
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// 0 = all instruction fetches enabled
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// 1 = no instruction fetches enabled.
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register_bit!(ractlr, xn, 12);
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/// MPU Region Size and Enable Registers
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pub struct RSER;
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wrap_reg!(rser);
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def_reg_r!(RSER, rser::Read, "mrc p15, 0, $0, c6, c1, 2");
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def_reg_w!(RSER, rser::Write, "mcr p15, 0, $0, c6, c1, 2");
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// enable region
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register_bit!(rser, enable, 0);
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// Defines the region size:
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// b00000 - b00011=Unpredictable
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// b00100 = 32 bytes
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// b00101 = 64 bytes
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// b00110 = 128 bytes
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// b00111 = 256 bytes
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// b01000 = 512 bytes
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// b01001 = 1KB
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// b01010 = 2KB
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// b01011 = 4KB
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// b01100 = 8KB
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// b01101 = 16KB
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// b01110 = 32KB
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// b01111 = 64KB
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// b10000 = 128KB
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// b10001 = 256KB
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// b10010 = 512KB
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// b10011 = 1MB
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// b10100 = 2MB
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// b10101 = 4MB
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// b10110 = 8MB
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// b10111 = 16MB
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// b11000 = 32MB
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// b11001 = 64MB
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// b11010 = 128MB
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// b11011 = 256MB
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// b11100 = 512MB
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// b11101 = 1GB
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// b11110 = 2GB
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// b11111 = 4GB
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register_bits!(rser, region_size, u8, 1, 5);
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// Each bit position represents a sub-region, 0-7.
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// Bit [8] corresponds to sub-region 0
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// ...
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// Bit [15] corresponds to sub-region 7
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// The meaning of each bit is:
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// 0 = address range is part of this region
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// 1 = address range is not part of this region
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register_bits!(rser, subregion_disable, u8, 8, 15);
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/// MPU Region Base Address Registers
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pub struct RBAR;
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wrap_reg!(rbar);
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def_reg_r!(RBAR, rbar::Read, "mrc p15, 0, $0, c6, c1, 0");
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def_reg_w!(RBAR, rbar::Write, "mcr p15, 0, $0, c6, c1, 0");
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// base address
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register_bits!(rbar, base_address, u32, 5, 31);
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// TODO: TCM registers (R5 TRM sec 4.3.23-25)
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