From 4168eb63a7e846863331ae4e656cfd82a867cca8 Mon Sep 17 00:00:00 2001 From: morgan Date: Tue, 19 Dec 2023 18:41:03 +0800 Subject: [PATCH] GIC: fix wrong core target config when enabling interrupt (#109) # Summary - Before the patch, an extra 1 is added to `target_cpu` and the interrupt will be configured to the wrong CPU target. | target_cpu | bits set before patch | bits set after patch | | -----------| ----------- | ----------- | | core0 | 0b10 (enable interrupt on core1) | 0b01 (enable interrupt on core0) | | core1 | 0b11 (enable interrupt on core0 & core1)| 0b10 (enable interrupt on core1) | - [Correct ICDIPTR Register configuration from AMD](https://docs.xilinx.com/r/en-US/ug585-zynq-7000-SoC-TRM/Software-Generated-Interrupts-SGI?tocId=0TsxAmy8MHRPDsayG96K1Q) Reviewed-on: https://git.m-labs.hk/M-Labs/zynq-rs/pulls/109 Co-authored-by: morgan Co-committed-by: morgan --- libboard_zynq/src/gic.rs | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/libboard_zynq/src/gic.rs b/libboard_zynq/src/gic.rs index fc962c6..c87adc2 100644 --- a/libboard_zynq/src/gic.rs +++ b/libboard_zynq/src/gic.rs @@ -115,7 +115,7 @@ impl InterruptController { let m = (id.0 >> 2) as usize; let n = (8 * (id.0 & 3)) as usize; unsafe { - self.mpcore.icdiptr[m].modify(|mut icdiptr| *icdiptr.set_bits(n..=n+1, target_cpu as u32 + 1)); + self.mpcore.icdiptr[m].modify(|mut icdiptr| *icdiptr.set_bits(n..=n+1, target_cpu as u32)); } // sensitivity