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zynq-rs
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i2c: conservative timing, avoid SCL/SDA races. Closes #83

This commit is contained in:
Sebastien Bourdeauducq 2021-06-25 16:26:04 +08:00
parent d18c77c0eb
commit 4159aab6c8
1 changed files with 3 additions and 0 deletions
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3
libboard_zynq/src/i2c/mod.rs
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@ -150,6 +150,7 @@ impl I2c {
self.sda_oe(true);
self.half_period();
self.scl_oe(true);
self.half_period();
// postcondition: SCL and SDA low
Ok(())
}
@ -188,6 +189,7 @@ impl I2c {
self.scl_oe(false);
self.half_period();
self.scl_oe(true);
self.half_period();
}
self.sda_oe(false);
self.half_period();
@ -196,6 +198,7 @@ impl I2c {
// Read ack/nack
let ack = !self.sda_i();
self.scl_oe(true);
self.half_period();
self.sda_oe(true);
// postcondition: SCL and SDA low