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zynq-rs
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fix typo

This commit is contained in:
morgan 2023-12-15 10:15:18 +08:00
parent 1b714a8ca0
commit 1df7d1bb7d
1 changed files with 3 additions and 3 deletions
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6
libboard_zynq/src/timer/global.rs
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@ -28,7 +28,7 @@ impl GlobalTimer {
// Start // Start
regs.global_timer_control.write( regs.global_timer_control.write(
mpcore::GlobalTimerControl::zeroed() mpcore::GlobalTimerControl::zeroed()
.prescaler((Self::get_prescalar() - 1) as u8) .prescaler((Self::get_prescaler() - 1) as u8)
.auto_increment_mode(true) .auto_increment_mode(true)
.timer_enable(true) .timer_enable(true)
); );
@ -40,7 +40,7 @@ impl GlobalTimer {
let mut regs = mpcore::RegisterBlock::mpcore(); let mut regs = mpcore::RegisterBlock::mpcore();
Self::reset(&mut regs); Self::reset(&mut regs);
let prescaler = Self::get_prescalar() as u64; let prescaler = Self::get_prescaler() as u64;
let clocks = Clocks::get(); let clocks = Clocks::get();
let increment_val:u32 = (interrupt_period_us * clocks.cpu_3x2x() as u64 / (1_000_000 * (prescaler + 1))) as u32; let increment_val:u32 = (interrupt_period_us * clocks.cpu_3x2x() as u64 / (1_000_000 * (prescaler + 1))) as u32;
@ -87,7 +87,7 @@ impl GlobalTimer {
); );
} }
fn get_prescalar() -> u32 { fn get_prescaler() -> u32 {
// find a prescaler value that matches CPU speed / 2 to us // find a prescaler value that matches CPU speed / 2 to us
let clocks = Clocks::get(); let clocks = Clocks::get();
let mut prescaler = clocks.cpu_3x2x() / 1_000_000; let mut prescaler = clocks.cpu_3x2x() / 1_000_000;