From 1a96a7550adf6af9cd0c1be8466db4b3f162904c Mon Sep 17 00:00:00 2001 From: Harry Ho Date: Thu, 13 Aug 2020 13:39:04 +0800 Subject: [PATCH] libboard_zynq: make RegisterBlock constructors more consistent --- experiments/src/main.rs | 10 +++++----- libboard_zynq/src/clocks/mod.rs | 8 ++++---- libboard_zynq/src/clocks/source.rs | 2 +- libboard_zynq/src/ddr/mod.rs | 2 +- libboard_zynq/src/ddr/regs.rs | 8 ++------ libboard_zynq/src/eth/regs.rs | 16 +++------------- libboard_zynq/src/flash/regs.rs | 10 +++------- libboard_zynq/src/i2c/mod.rs | 4 ++-- libboard_zynq/src/i2c/regs.rs | 6 +++--- libboard_zynq/src/mpcore.rs | 2 +- libboard_zynq/src/slcr.rs | 4 ++-- libboard_zynq/src/timer/global.rs | 4 ++-- libsupport_zynq/src/boot.rs | 4 ++-- 13 files changed, 31 insertions(+), 49 deletions(-) diff --git a/experiments/src/main.rs b/experiments/src/main.rs index 2e44f83..6941d4b 100644 --- a/experiments/src/main.rs +++ b/experiments/src/main.rs @@ -56,7 +56,7 @@ static CORE1_RESTART: AtomicBool = AtomicBool::new(false); #[naked] pub unsafe extern "C" fn IRQ() { if MPIDR.read().cpu_id() == 1{ - let mpcore = mpcore::RegisterBlock::new(); + let mpcore = mpcore::RegisterBlock::mpcore(); let mut gic = gic::InterruptController::gic(mpcore); let id = gic.get_interrupt_id(); if id.0 == 0 { @@ -75,7 +75,7 @@ pub unsafe extern "C" fn IRQ() { } pub fn restart_core1() { - let mut interrupt_controller = gic::InterruptController::gic(mpcore::RegisterBlock::new()); + let mut interrupt_controller = gic::InterruptController::gic(mpcore::RegisterBlock::mpcore()); CORE1_RESTART.store(true, Ordering::Relaxed); interrupt_controller.send_sgi(gic::InterruptId(0), gic::CPUCore::Core1.into()); while CORE1_RESTART.load(Ordering::Relaxed) { @@ -87,7 +87,7 @@ pub fn restart_core1() { pub fn main_core0() { // zynq::clocks::CpuClocks::enable_io(1_250_000_000); println!("\nzc706 main"); - let mut interrupt_controller = gic::InterruptController::gic(mpcore::RegisterBlock::new()); + let mut interrupt_controller = gic::InterruptController::gic(mpcore::RegisterBlock::mpcore()); interrupt_controller.enable_interrupts(); // ps7_init::apply(); libboard_zynq::stdio::drop_uart(); @@ -97,7 +97,7 @@ pub fn main_core0() { info!( "Boot mode: {:?}", - zynq::slcr::RegisterBlock::new() + zynq::slcr::RegisterBlock::slcr() .boot_mode .read() .boot_mode_pins() @@ -331,7 +331,7 @@ static DONE: Mutex = Mutex::new(false); #[no_mangle] pub fn main_core1() { println!("Hello from core1!"); - let mut interrupt_controller = gic::InterruptController::gic(mpcore::RegisterBlock::new()); + let mut interrupt_controller = gic::InterruptController::gic(mpcore::RegisterBlock::mpcore()); interrupt_controller.enable_interrupts(); let req = unsafe { &mut CORE1_REQ.1 }; let res = unsafe { &mut CORE1_RES.0 }; diff --git a/libboard_zynq/src/clocks/mod.rs b/libboard_zynq/src/clocks/mod.rs index 925768c..ee9cebd 100644 --- a/libboard_zynq/src/clocks/mod.rs +++ b/libboard_zynq/src/clocks/mod.rs @@ -14,7 +14,7 @@ enum CpuClockMode { impl CpuClockMode { pub fn get() -> Self { - let regs = slcr::RegisterBlock::new(); + let regs = slcr::RegisterBlock::slcr(); if regs.clk_621_true.read().clk_621_true() { CpuClockMode::C621 } else { @@ -59,7 +59,7 @@ impl Clocks { } pub fn cpu_6x4x(&self) -> u32 { - let slcr = slcr::RegisterBlock::new(); + let slcr = slcr::RegisterBlock::slcr(); let arm_clk_ctrl = slcr.arm_clk_ctrl.read(); let pll = match arm_clk_ctrl.srcsel() { ArmPllSource::ArmPll => self.arm, @@ -92,7 +92,7 @@ impl Clocks { } pub fn uart_ref_clk(&self) -> u32 { - let regs = slcr::RegisterBlock::new(); + let regs = slcr::RegisterBlock::slcr(); let uart_clk_ctrl = regs.uart_clk_ctrl.read(); let pll = match uart_clk_ctrl.srcsel() { slcr::PllSource::ArmPll => @@ -106,7 +106,7 @@ impl Clocks { } pub fn sdio_ref_clk(&self) -> u32 { - let regs = slcr::RegisterBlock::new(); + let regs = slcr::RegisterBlock::slcr(); let sdio_clk_ctrl = regs.sdio_clk_ctrl.read(); let pll = match sdio_clk_ctrl.srcsel() { slcr::PllSource::ArmPll => diff --git a/libboard_zynq/src/clocks/source.rs b/libboard_zynq/src/clocks/source.rs index 7f091e5..18348c5 100644 --- a/libboard_zynq/src/clocks/source.rs +++ b/libboard_zynq/src/clocks/source.rs @@ -44,7 +44,7 @@ pub trait ClockSource { /// get configured frequency fn freq() -> u32 { - let mut slcr = slcr::RegisterBlock::new(); + let mut slcr = slcr::RegisterBlock::slcr(); let (pll_ctrl, _, _) = Self::pll_regs(&mut slcr); u32::from(pll_ctrl.read().pll_fdiv()) * PS_CLK } diff --git a/libboard_zynq/src/ddr/mod.rs b/libboard_zynq/src/ddr/mod.rs index b6d9a57..66a1098 100644 --- a/libboard_zynq/src/ddr/mod.rs +++ b/libboard_zynq/src/ddr/mod.rs @@ -27,7 +27,7 @@ impl DdrRam { Self::calibrate_iob_impedance(&clocks); Self::configure_iob(); - let regs = unsafe { regs::RegisterBlock::new() }; + let regs = unsafe { regs::RegisterBlock::ddrc() }; let mut ddr = DdrRam { regs }; ddr.configure(); ddr.reset_ddrc(); diff --git a/libboard_zynq/src/ddr/regs.rs b/libboard_zynq/src/ddr/regs.rs index 53f67cb..3213ceb 100644 --- a/libboard_zynq/src/ddr/regs.rs +++ b/libboard_zynq/src/ddr/regs.rs @@ -1,6 +1,6 @@ use volatile_register::{RO, RW}; -use libregister::{register, register_bit, register_bits, register_bits_typed}; +use libregister::{register, register_at, register_bit, register_bits, register_bits_typed}; #[allow(unused)] #[derive(Clone, Copy)] @@ -158,11 +158,7 @@ pub struct RegisterBlock { pub lpddr_ctrl3: RW, } -impl RegisterBlock { - pub unsafe fn new() -> &'static mut Self { - &mut *(0xF8006000 as *mut _) - } -} +register_at!(RegisterBlock, 0xF8006000, ddrc); register!(ddrc_ctrl, DdrcCtrl, RW, u32); register_bit!(ddrc_ctrl, diff --git a/libboard_zynq/src/eth/regs.rs b/libboard_zynq/src/eth/regs.rs index b3081be..e0821b9 100644 --- a/libboard_zynq/src/eth/regs.rs +++ b/libboard_zynq/src/eth/regs.rs @@ -1,6 +1,6 @@ use volatile_register::{RO, WO, RW}; -use libregister::{register, register_bit, register_bits, register_bits_typed}; +use libregister::{register, register_at, register_bit, register_bits, register_bits_typed}; #[repr(C)] pub struct RegisterBlock { @@ -110,18 +110,8 @@ pub struct RegisterBlock { pub design_cfg5: RO, } -impl RegisterBlock { - const GEM0: *mut Self = 0xE000B000 as *mut _; - const GEM1: *mut Self = 0xE000C000 as *mut _; - - pub fn gem0() -> &'static mut Self { - unsafe { &mut *Self::GEM0 } - } - - pub fn gem1() -> &'static mut Self { - unsafe { &mut *Self::GEM1 } - } -} +register_at!(RegisterBlock, 0xE000B000, gem0); +register_at!(RegisterBlock, 0xE000C000, gem1); register!(net_ctrl, NetCtrl, RW, u32); register_bit!(net_ctrl, loopback_local, 1); diff --git a/libboard_zynq/src/flash/regs.rs b/libboard_zynq/src/flash/regs.rs index f98eb47..9a62dac 100644 --- a/libboard_zynq/src/flash/regs.rs +++ b/libboard_zynq/src/flash/regs.rs @@ -1,6 +1,6 @@ use volatile_register::{RO, WO, RW}; -use libregister::{register, register_bit, register_bits}; +use libregister::{register, register_at, register_bit, register_bits}; #[repr(C)] pub struct RegisterBlock { @@ -30,13 +30,9 @@ pub struct RegisterBlock { pub mod_id: RW, } -impl RegisterBlock { - const BASE_ADDRESS: *mut Self = 0xE000D000 as *mut _; +const BASE_ADDRESS: u32 = 0xE000D000; - pub fn qspi() -> &'static mut Self { - unsafe { &mut *Self::BASE_ADDRESS } - } -} +register_at!(RegisterBlock, 0xE000D000, qspi); register!(config, Config, RW, u32); register_bit!(config, diff --git a/libboard_zynq/src/i2c/mod.rs b/libboard_zynq/src/i2c/mod.rs index d701b39..c0b6ad8 100644 --- a/libboard_zynq/src/i2c/mod.rs +++ b/libboard_zynq/src/i2c/mod.rs @@ -8,7 +8,7 @@ use embedded_hal::timer::CountDown; use libregister::{RegisterR, RegisterRW, RegisterW}; pub struct I2c { - regs: regs::RegisterWrapper, + regs: regs::RegisterBlock, count_down: super::timer::global::CountDown } @@ -43,7 +43,7 @@ impl I2c { fn i2c_common(gpio_output_mask: u16) -> Self { // Setup register block let self_ = Self { - regs: regs::RegisterWrapper::new(), + regs: regs::RegisterBlock::i2c(), count_down: unsafe { super::timer::GlobalTimer::get() }.countdown() }; diff --git a/libboard_zynq/src/i2c/regs.rs b/libboard_zynq/src/i2c/regs.rs index d2a59e6..b657bc5 100644 --- a/libboard_zynq/src/i2c/regs.rs +++ b/libboard_zynq/src/i2c/regs.rs @@ -21,15 +21,15 @@ use libregister::{ // Current compatibility: // zc706: GPIO 50, 51 == SCL, SDA -pub struct RegisterWrapper { +pub struct RegisterBlock { pub gpio_output_mask: &'static mut GPIOOutputMask, pub gpio_input: &'static mut GPIOInput, pub gpio_direction: &'static mut GPIODirection, pub gpio_output_enable: &'static mut GPIOOutputEnable, } -impl RegisterWrapper { - pub fn new() -> Self { +impl RegisterBlock { + pub fn i2c() -> Self { Self { gpio_output_mask: GPIOOutputMask::new(), gpio_input: GPIOInput::new(), diff --git a/libboard_zynq/src/mpcore.rs b/libboard_zynq/src/mpcore.rs index 8a55d5b..10d3eac 100644 --- a/libboard_zynq/src/mpcore.rs +++ b/libboard_zynq/src/mpcore.rs @@ -138,7 +138,7 @@ pub struct RegisterBlock { pub icdsgir: ICDSGIR, } -register_at!(RegisterBlock, 0xF8F00000, new); +register_at!(RegisterBlock, 0xF8F00000, mpcore); register!(value_register, ValueRegister, RW, u32); register_bits!(value_register, value, u32, 0, 31); diff --git a/libboard_zynq/src/slcr.rs b/libboard_zynq/src/slcr.rs index 771e212..eb4b550 100644 --- a/libboard_zynq/src/slcr.rs +++ b/libboard_zynq/src/slcr.rs @@ -253,12 +253,12 @@ pub struct RegisterBlock { pub ddriob_dci_ctrl: DdriobDciCtrl, pub ddriob_dci_status: DdriobDciStatus, } -register_at!(RegisterBlock, 0xF8000000, new); +register_at!(RegisterBlock, 0xF8000000, slcr); impl RegisterBlock { /// Required to modify any sclr register pub fn unlocked R, R>(mut f: F) -> R { - let mut self_ = Self::new(); + let mut self_ = Self::slcr(); self_.slcr_unlock.unlock(); let r = f(&mut self_); self_.slcr_lock.lock(); diff --git a/libboard_zynq/src/timer/global.rs b/libboard_zynq/src/timer/global.rs index 1875e76..6ace973 100644 --- a/libboard_zynq/src/timer/global.rs +++ b/libboard_zynq/src/timer/global.rs @@ -16,13 +16,13 @@ pub struct GlobalTimer { impl GlobalTimer { /// Get the potentially uninitialized timer pub unsafe fn get() -> GlobalTimer { - let regs = mpcore::RegisterBlock::new(); + let regs = mpcore::RegisterBlock::mpcore(); GlobalTimer { regs } } /// Get the timer with a reset pub fn start() -> GlobalTimer { - let mut regs = mpcore::RegisterBlock::new(); + let mut regs = mpcore::RegisterBlock::mpcore(); Self::reset(&mut regs); GlobalTimer { regs } } diff --git a/libsupport_zynq/src/boot.rs b/libsupport_zynq/src/boot.rs index b6a1bbc..724a31d 100644 --- a/libsupport_zynq/src/boot.rs +++ b/libsupport_zynq/src/boot.rs @@ -43,7 +43,7 @@ pub unsafe extern "C" fn Reset() -> ! { unsafe fn boot_core0() -> ! { l1_cache_init(); - let mpcore = mpcore::RegisterBlock::new(); + let mpcore = mpcore::RegisterBlock::mpcore(); mpcore.scu_invalidate.invalidate_all_cores(); zero_bss(&mut __bss_start, &mut __bss_end); @@ -68,7 +68,7 @@ unsafe fn boot_core0() -> ! { unsafe fn boot_core1() -> ! { l1_cache_init(); - let mpcore = mpcore::RegisterBlock::new(); + let mpcore = mpcore::RegisterBlock::mpcore(); mpcore.scu_invalidate.invalidate_core1(); let mmu_table = mmu::L1Table::get();