diff --git a/README.md b/README.md
index 0744d7b..0c87a8a 100644
--- a/README.md
+++ b/README.md
@@ -38,7 +38,7 @@ openocd -f zc706.cfg
 ### Running on the Cora Z7-10
 
 ```shell
-nix-shell --command "cd experiments && cargo xbuild --release --no-default-features --features=target_cora_z7_10"
+nix-shell --command "cd experiments && cargo xbuild --release --no-default-features --features=target_coraz7"
 cd openocd
 openocd -f cora-z7-10.cfg
 ```
diff --git a/experiments/Cargo.toml b/experiments/Cargo.toml
index ee4b5b0..90c242b 100644
--- a/experiments/Cargo.toml
+++ b/experiments/Cargo.toml
@@ -7,7 +7,7 @@ edition = "2018"
 
 [features]
 target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706"]
-target_cora_z7_10 = ["libboard_zynq/target_cora_z7_10", "libsupport_zynq/target_cora_z7_10"]
+target_coraz7 = ["libboard_zynq/target_coraz7", "libsupport_zynq/target_coraz7"]
 target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya"]
 default = ["target_zc706"]
 
diff --git a/experiments/src/main.rs b/experiments/src/main.rs
index df53b43..47f4753 100644
--- a/experiments/src/main.rs
+++ b/experiments/src/main.rs
@@ -107,7 +107,7 @@ pub fn main_core0() {
 
     #[cfg(feature = "target_zc706")]
     const CPU_FREQ: u32 = 800_000_000;
-    #[cfg(feature = "target_cora_z7_10")]
+    #[cfg(feature = "target_coraz7")]
     const CPU_FREQ: u32 = 650_000_000;
     #[cfg(feature = "target_redpitaya")]
     const CPU_FREQ: u32 = 800_000_000;
@@ -120,7 +120,7 @@ pub fn main_core0() {
         IoPll::setup(1_000_000_000);
         libboard_zynq::stdio::drop_uart();
     }
-    #[cfg(feature = "target_cora_z7_10")]
+    #[cfg(feature = "target_coraz7")]
     {
         IoPll::setup(1_000_000_000);
         libboard_zynq::stdio::drop_uart();
diff --git a/libboard_zynq/Cargo.toml b/libboard_zynq/Cargo.toml
index 45b259a..a2eb3eb 100644
--- a/libboard_zynq/Cargo.toml
+++ b/libboard_zynq/Cargo.toml
@@ -7,7 +7,7 @@ edition = "2018"
 
 [features]
 target_zc706 = []
-target_cora_z7_10 = []
+target_coraz7 = []
 target_redpitaya = []
 ipv6 = [ "smoltcp/proto-ipv6" ]
 
diff --git a/libboard_zynq/src/clocks/source.rs b/libboard_zynq/src/clocks/source.rs
index 93f6161..5334fb1 100644
--- a/libboard_zynq/src/clocks/source.rs
+++ b/libboard_zynq/src/clocks/source.rs
@@ -4,7 +4,7 @@ use super::slcr;
 
 #[cfg(feature = "target_zc706")]
 pub const PS_CLK: u32 = 33_333_333;
-#[cfg(feature = "target_cora_z7_10")]
+#[cfg(feature = "target_coraz7")]
 pub const PS_CLK: u32 = 50_000_000;
 #[cfg(feature = "target_redpitaya")]
 pub const PS_CLK: u32 = 33_333_333;
diff --git a/libboard_zynq/src/ddr/mod.rs b/libboard_zynq/src/ddr/mod.rs
index 769196c..f70175f 100644
--- a/libboard_zynq/src/ddr/mod.rs
+++ b/libboard_zynq/src/ddr/mod.rs
@@ -12,7 +12,7 @@ mod regs;
 /// Micron MT41J256M8HX-15E: 667 MHz DDR3
 const DDR_FREQ: u32 = 666_666_666;
 
-#[cfg(feature = "target_cora_z7_10")]
+#[cfg(feature = "target_coraz7")]
 /// Micron MT41K256M16HA-125: 800 MHz DDR3L, max supported 533 MHz
 const DDR_FREQ: u32 = 525_000_000;
 
@@ -144,13 +144,13 @@ impl DdrRam {
                 .output_en(slcr::DdriobOutputEn::Obuf);
             #[cfg(feature = "target_zc706")]
             let data1_config = data0_config.clone();
-            #[cfg(feature = "target_cora_z7_10")]
+            #[cfg(feature = "target_coraz7")]
             let data0_config = slcr::DdriobConfig::zeroed()
                 .inp_type(slcr::DdriobInputType::VrefDifferential)
                 .term_en(true)
                 .dci_type(slcr::DdriobDciType::Termination)
                 .output_en(slcr::DdriobOutputEn::Obuf);
-            #[cfg(feature = "target_cora_z7_10")]
+            #[cfg(feature = "target_coraz7")]
             let data1_config = slcr::DdriobConfig::zeroed()
                 .pullup_en(true);
             #[cfg(feature = "target_redpitaya")]
@@ -173,13 +173,13 @@ impl DdrRam {
                 .output_en(slcr::DdriobOutputEn::Obuf);
             #[cfg(feature = "target_zc706")]
             let diff1_config = diff0_config.clone();
-            #[cfg(feature = "target_cora_z7_10")]
+            #[cfg(feature = "target_coraz7")]
             let diff0_config = slcr::DdriobConfig::zeroed()
                 .inp_type(slcr::DdriobInputType::Differential)
                 .term_en(true)
                 .dci_type(slcr::DdriobDciType::Termination)
                 .output_en(slcr::DdriobOutputEn::Obuf);
-            #[cfg(feature = "target_cora_z7_10")]
+            #[cfg(feature = "target_coraz7")]
             let diff1_config = slcr::DdriobConfig::zeroed()
                 .pullup_en(true);
             #[cfg(feature = "target_redpitaya")]
@@ -207,7 +207,7 @@ impl DdrRam {
                 slcr.ddriob_drive_slew_clock.write(0x00F9861C);
             }
 
-            #[cfg(feature = "target_cora_z7_10")]
+            #[cfg(feature = "target_coraz7")]
             slcr.ddriob_ddr_ctrl.modify(|_, w| w
                     .vref_int_en(false)
                     .vref_ext_en_lower(true)
@@ -232,7 +232,7 @@ impl DdrRam {
     }
 
     fn configure(&mut self) {
-        #[cfg(feature = "target_cora_z7_10")]
+        #[cfg(feature = "target_coraz7")]
         self.regs.dram_param0.write(
             regs::DramParam0::zeroed()
                 .t_rc(0x1a)
@@ -295,11 +295,11 @@ impl DdrRam {
                 .emr(0x4)
         );
 
-        #[cfg(feature = "target_cora_z7_10")]
+        #[cfg(feature = "target_coraz7")]
         self.regs.phy_configs[2].modify(
             |_, w| w.data_slice_in_use(false)
         );
-        #[cfg(feature = "target_cora_z7_10")]
+        #[cfg(feature = "target_coraz7")]
         self.regs.phy_configs[3].modify(
             |_, w| w.data_slice_in_use(false)
         );
@@ -351,7 +351,7 @@ impl DdrRam {
                 .gatelvl_init_ratio(0xee)
         );
 
-        #[cfg(feature = "target_cora_z7_10")]
+        #[cfg(feature = "target_coraz7")]
         self.regs.reg_64.modify(
             |_, w| w
                 .phy_ctrl_slave_ratio(0x100)
@@ -387,7 +387,7 @@ impl DdrRam {
     fn reset_ddrc<F: FnMut(&mut Self)>(&mut self, mut f: F) {
         #[cfg(feature = "target_zc706")]
         let width = regs::DataBusWidth::Width32bit;
-        #[cfg(feature = "target_cora_z7_10")]
+        #[cfg(feature = "target_coraz7")]
         let width = regs::DataBusWidth::Width16bit;
         #[cfg(feature = "target_redpitaya")]
         let width = regs::DataBusWidth::Width16bit;
@@ -405,7 +405,7 @@ impl DdrRam {
             self.regs.dram_addr_map_col.write(0xFFF00000);
             self.regs.dram_addr_map_row.write(0x0F666666);
         }
-        #[cfg(any(feature = "target_cora_z7_10", feature = "target_redpitaya"))]
+        #[cfg(any(feature = "target_coraz7", feature = "target_redpitaya"))]
         unsafe {
             // row/column address bits
             self.regs.dram_addr_map_bank.write(0x00000666);
@@ -437,7 +437,7 @@ impl DdrRam {
         // filtering address map
         #[cfg(feature = "target_zc706")]
         let megabytes = 1023;
-        #[cfg(feature = "target_cora_z7_10")]
+        #[cfg(feature = "target_coraz7")]
         let megabytes = 512;
         #[cfg(feature = "target_redpitaya")]
         let megabytes = 512;
diff --git a/libboard_zynq/src/sdio/mod.rs b/libboard_zynq/src/sdio/mod.rs
index 1fc4415..3b4678b 100644
--- a/libboard_zynq/src/sdio/mod.rs
+++ b/libboard_zynq/src/sdio/mod.rs
@@ -105,7 +105,7 @@ impl Sdio {
                 );
             }
             // cora card detect pin
-            #[cfg(feature = "target_cora_z7_10")]
+            #[cfg(feature = "target_coraz7")]
             {
                 unsafe {
                     slcr.sd0_wp_cd_sel.write(47 << 16);
diff --git a/libboard_zynq/src/stdio.rs b/libboard_zynq/src/stdio.rs
index 39ba61f..667948b 100644
--- a/libboard_zynq/src/stdio.rs
+++ b/libboard_zynq/src/stdio.rs
@@ -45,7 +45,7 @@ impl DerefMut for LazyUart {
     fn deref_mut(&mut self) -> &mut Uart {
         match self {
             LazyUart::Uninitialized => {
-                #[cfg(any(feature = "target_cora_z7_10", feature = "target_redpitaya"))]
+                #[cfg(any(feature = "target_coraz7", feature = "target_redpitaya"))]
                 let uart = Uart::uart0(UART_RATE);
                 #[cfg(feature = "target_zc706")]
                 let uart = Uart::uart1(UART_RATE);
diff --git a/libboard_zynq/src/uart/mod.rs b/libboard_zynq/src/uart/mod.rs
index 6a63471..1ab6f3f 100644
--- a/libboard_zynq/src/uart/mod.rs
+++ b/libboard_zynq/src/uart/mod.rs
@@ -13,7 +13,7 @@ pub struct Uart {
 }
 
 impl Uart {
-    #[cfg(any(feature = "target_cora_z7_10", feature = "target_redpitaya"))]
+    #[cfg(any(feature = "target_coraz7", feature = "target_redpitaya"))]
     pub fn uart0(baudrate: u32) -> Self {
         slcr::RegisterBlock::unlocked(|slcr| {
             // Route UART 0 RxD/TxD Signals to MIO Pins
diff --git a/libconfig/Cargo.toml b/libconfig/Cargo.toml
index c3356ab..cb3d9d5 100644
--- a/libconfig/Cargo.toml
+++ b/libconfig/Cargo.toml
@@ -12,6 +12,6 @@ log = "0.4"
 
 [features]
 target_zc706 = []
-target_cora_z7_10 = []
+target_coraz7 = []
 target_redpitaya = []
 ipv6 = []
diff --git a/libconfig/src/net_settings.rs b/libconfig/src/net_settings.rs
index 9439dbc..6d6a40f 100644
--- a/libconfig/src/net_settings.rs
+++ b/libconfig/src/net_settings.rs
@@ -35,9 +35,9 @@ pub fn get_adresses(cfg: &Config) -> NetAddresses {
     let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x52]);
     #[cfg(feature = "target_zc706")]
     let mut ipv4_addr = IpAddress::v4(192, 168, 1, 52);
-    #[cfg(feature = "target_cora_z7_10")]
+    #[cfg(feature = "target_coraz7")]
     let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x54]);
-    #[cfg(feature = "target_cora_z7_10")]
+    #[cfg(feature = "target_coraz7")]
     let mut ipv4_addr = IpAddress::v4(192, 168, 1, 54);
     #[cfg(feature = "target_redpitaya")]
     let mut hardware_addr = EthernetAddress([0x02, 0x00, 0x00, 0x00, 0x00, 0x55]);
diff --git a/libcortex_a9/Cargo.toml b/libcortex_a9/Cargo.toml
index 11f03d3..b140207 100644
--- a/libcortex_a9/Cargo.toml
+++ b/libcortex_a9/Cargo.toml
@@ -6,7 +6,7 @@ edition = "2018"
 
 [features]
 target_zc706 = []
-target_cora_z7_10 = []
+target_coraz7 = []
 target_redpitaya = []
 power_saving = []
 default = ["target_zc706"]
diff --git a/libsupport_zynq/Cargo.toml b/libsupport_zynq/Cargo.toml
index 950a716..c7c5118 100644
--- a/libsupport_zynq/Cargo.toml
+++ b/libsupport_zynq/Cargo.toml
@@ -7,7 +7,7 @@ edition = "2018"
 
 [features]
 target_zc706 = ["libboard_zynq/target_zc706"]
-target_cora_z7_10 = ["libboard_zynq/target_cora_z7_10"]
+target_coraz7 = ["libboard_zynq/target_coraz7"]
 target_redpitaya = ["libboard_zynq/target_redpitaya"]
 panic_handler = []
 dummy_irq_handler = []
diff --git a/szl/Cargo.toml b/szl/Cargo.toml
index 43d7382..00691f5 100644
--- a/szl/Cargo.toml
+++ b/szl/Cargo.toml
@@ -7,7 +7,7 @@ edition = "2018"
 
 [features]
 target_zc706 = ["libboard_zynq/target_zc706", "libsupport_zynq/target_zc706", "libconfig/target_zc706"]
-target_cora_z7_10 = ["libboard_zynq/target_cora_z7_10", "libsupport_zynq/target_cora_z7_10", "libconfig/target_cora_z7_10"]
+target_coraz7 = ["libboard_zynq/target_coraz7", "libsupport_zynq/target_coraz7", "libconfig/target_coraz7"]
 target_redpitaya = ["libboard_zynq/target_redpitaya", "libsupport_zynq/target_redpitaya", "libconfig/target_redpitaya"]
 default = ["target_zc706"]