libboard_zynq: fix access to "full" 1022 MB on target_zc706

libboard_zynq/src/ddr/mod.rs

@@ -183,6 +183,14 @@ impl DdrRam {
 
     /// Reset DDR controller
     fn reset_ddrc(&mut self) {
+        #[cfg(feature = "target_zc706")]
+        unsafe {
+            // row/column address bits
+            self.regs.dram_addr_map_bank.write(0x00000777);
+            self.regs.dram_addr_map_col.write(0xFFF00000);
+            self.regs.dram_addr_map_row.write(0x0F666666);
+        }
+
         #[cfg(feature = "target_zc706")]
         let width = regs::DataBusWidth::Width32bit;
         #[cfg(feature = "target_cora_z7_10")]
@@ -209,9 +217,11 @@ impl DdrRam {
         0x0010_0000 as *mut _
     }
 
+    /// actually there's 1 MB more but starting at 0x0000_0000
+    /// overlaps with OCM.
     pub fn size(&self) -> usize {
         #[cfg(feature = "target_zc706")]
-        let megabytes = 511;
+        let megabytes = 1022;
         #[cfg(feature = "target_cora_z7_10")]
         let megabytes = 511;
 

libcortex_a9/src/mmu.rs

@@ -123,7 +123,7 @@ impl L1Table {
             bufferable: true,
         });
         /* (DDR cacheable) */
-        for ddr in 1..=0x1ff {
+        for ddr in 1..=0x3ff {
             self.direct_mapped_section(ddr, L1Section {
                 global: true,
                 shareable: true,
@@ -135,19 +135,6 @@ impl L1Table {
                 bufferable: false,
             });
         }
-        /* (unassigned/reserved). */
-        for undef in 0x1ff..=0x3ff {
-            self.direct_mapped_section(undef, L1Section {
-                global: false,
-                shareable: false,
-                access: AccessPermissions::PermissionFault,
-                tex: 0,
-                domain: 0,
-                exec: false,
-                cacheable: false,
-                bufferable: false,
-            });
-        }
         /* 0x40000000 - 0x7fffffff (FPGA slave0) */
         for fpga_slave in 0x400..=0x7ff {
             self.direct_mapped_section(fpga_slave, L1Section {