morgan 8be1abe80b | ||
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src | ||
.gitignore | ||
README.md | ||
flake.lock | ||
flake.nix | ||
poetry.lock | ||
pyproject.toml |
README.md
WRPLL simulation
A time domain simulation for WRPLL
Installation
Poetry:
poetry install --no-root
poetry run jupyter lab
Poetry shell:
poetry install --no-root
poetry shell
Nix:
nix develop
Quick start
-
Three notebook examples are included
helper_PLL_example.ipynb
: helper PLL onlymain_PLL_example.ipynb
: main PLL only with a user specific helper frequencyboth_PLL_example.ipynb
: main and helper PLL
-
RAM usage and execution time estimate for simulation ONLY
-
100,000,000 time steps: 6GiB RAM and 12 seconds
-
200,000,000 time steps: 11GiB RAM and 20 seconds
-
300,000,000 time steps: 16GiB RAM and 35 seconds
-
WRPLL formulas
-
Assume the difference between
f_{main}, f_{gtx}
is very small-
Let
f_{in} = f_{main} = f_{gtx}
-
f_{helper} = f_{in} * \dfrac{N-1}{N}
-
f_{beat} = f_{in} - f_{helper} = \dfrac{f_{in}}{N}
-
-
Main and helper Si549 DCXO ADPLL setting
ADPLL = \dfrac{\Delta f_{outppm}}{0.0001164}
Limitation
- The simulation is missing the switching delay of "receiving ADPLL -> DCXO output starting to change"
- The white noise is used to simulate jitter which may result in higher phase noise