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morgan 0b724e84da wrapper: QoL improvement time array is generated inside of wrapper set default value for RNGs and ddmtd config adpll_write_period and start_up_delay argument use seconds as their unit freq_diff_error RNG now used the seed argument and uniform RNG		2023-12-12 13:33:02 +08:00
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WRPLL simulation

A time domain simulation for WRPLL

Installing dependencies

nix develop

python -m venv .venv
source .venv/bin/activate
(venv) pip install -r requirements.txt

Three notebook examples are included
1. helper_PLL_example.ipynb : helper PLL only
2. main_PLL_example.ipynb : main PLL only with a user specific helper frequency
3. both_PLL_example.ipynb : main and helper PLL
RAM usage and execution time estimate for simulation ONLY
1. 100,000,000 time steps: 6GiB RAM and 12 seconds
2. 200,000,000 time steps: 11GiB RAM and 20 seconds
3. 300,000,000 time steps: 16GiB RAM and 35 seconds

WRPLL formulas

Assume the difference between f_{main}, f_{gtx} is very small
- Let f_{in} = f_{main} = f_{gtx}
- f_{helper} = f_{in} * \dfrac{N-1}{N}
- f_{beat} = f_{in} - f_{helper} = \dfrac{f_{in}}{N}
Main and helper Si549 DCXO ADPLL setting
- ADPLL = \dfrac{\Delta f_{outppm}}{0.0001164}

As the simulation is not cycle nor delay accurate, there will be more glitches than the hardware implementation