time array is generated inside of wrapper
set default value for RNGs and ddmtd config
adpll_write_period and start_up_delay argument use seconds as their unit
freq_diff_error RNG now used the seed argument and uniform RNG
wave_gen: add square wave with jitter generator
sim: add WRPLL gateware and firmware simulation
sim: add PID for main and helper PLL
sim: add options to choose PLL modes
sim: add cycle slip compensation for helper PLL
sim: optimize execution time with numba jit