diff --git a/src/sim.py b/src/sim.py
index 7cfb32b..a20bc34 100644
--- a/src/sim.py
+++ b/src/sim.py
@@ -22,6 +22,7 @@ def simulation_jit(
     base_adpll,
     N,
     adpll_write_period,
+    i2c_comm_delay,
     blind_period,
     start_up_delay,
     helper_init_freq=0
@@ -94,11 +95,13 @@ def simulation_jit(
     period_err = last_period_err = 0
     h_prop = h_integrator = h_derivative = 0
     h_adpll = base_adpll
+    h_i2c_active_index = 0
     period_colr_arm = h_i2c_active = False
 
     phase_err = last_phase_err = 0
     m_prop = m_integrator = m_derivative = 0
     m_adpll = base_adpll
+    m_i2c_active_index = 0
     phase_colr_arm = m_i2c_active = False
 
     adpll_max = 8161512
@@ -158,6 +161,9 @@ def simulation_jit(
 
         if i > start_up_delay:
 
+            if i % adpll_write_period == 0:
+                period_colr_arm = phase_colr_arm = True
+
             # Firmware filters
 
             if period_colr_arm and period_collector_r:
@@ -172,7 +178,7 @@ def simulation_jit(
 
                     h_adpll = clip(int(base_adpll + h_prop + h_integrator + h_derivative), -adpll_max, adpll_max)
                     last_period_err = period_err
-                    helper_freq = dcxo_freq * (1 + h_adpll * 0.0001164 / 1_000_000) * ((N-1) / N)
+                    h_i2c_active_index = i
                     h_i2c_active = True
 
             if phase_colr_arm and phase_collector_r:
@@ -191,11 +197,19 @@ def simulation_jit(
 
                     m_adpll = clip(int(base_adpll + m_prop + m_integrator + m_derivative), -adpll_max, adpll_max)
                     last_phase_err = phase_err
-                    main_freq = dcxo_freq * (1 + m_adpll * 0.0001164 / 1_000_000)
+
+                    m_i2c_active_index = i
                     m_i2c_active = True
 
-            if i % adpll_write_period == 0:
-                period_colr_arm = phase_colr_arm = True
+            # i2c communication delay
+
+            if h_i2c_active and i >= i2c_comm_delay + h_i2c_active_index:
+                helper_freq = dcxo_freq * (1 + h_adpll * 0.0001164 / 1_000_000) * ((N-1) / N)
+                h_i2c_active = False
+
+            if m_i2c_active and i >= i2c_comm_delay + m_i2c_active_index:
+                main_freq = dcxo_freq * (1 + m_adpll * 0.0001164 / 1_000_000)
+                m_i2c_active = False
 
         last_helper = helper[i]
 
diff --git a/src/wrpll.py b/src/wrpll.py
index 873ad1a..c29805b 100644
--- a/src/wrpll.py
+++ b/src/wrpll.py
@@ -15,6 +15,7 @@ class WRPLL_simulator():
         gtx_freq,
         adpll_write_period,
         start_up_delay,
+        i2c_comm_delay=85.6e-6,
         gtx_jitter=370e-15,
         dcxo_freq=125_000_000,
         dcxo_jitter=95e-15,
@@ -50,6 +51,7 @@ class WRPLL_simulator():
         self.base_adpll = int(freq_diff * (1 / dcxo_freq) * (1e6 / 0.0001164))
 
         # sim config
+        self.i2c_comm_delay = int(i2c_comm_delay/timestep)
         self.blind_period = blind_period
         self.adpll_write_period = int(adpll_write_period/timestep)
         self.start_up_delay = int(start_up_delay/timestep)
@@ -89,6 +91,7 @@ class WRPLL_simulator():
             self.base_adpll,
             self.N,
             self.adpll_write_period,
+            self.i2c_comm_delay,
             self.blind_period,
             self.start_up_delay,
             self.helper_init_freq