diff --git a/src/wrpll_simulation/config.py b/src/wrpll_simulation/config.py
index ae54754..80bca01 100644
--- a/src/wrpll_simulation/config.py
+++ b/src/wrpll_simulation/config.py
@@ -51,6 +51,9 @@ class Timesim_Config(object):
         helper_PI: PI_Config,
         main_PI: PI_Config,
         has_jitter: bool,
+        step_input_time: float64,
+        step_frequency: float64,
+        step_phase: float64,
     ):
         # jitter << timestep_size
         # otherwise simulation will add negative phase to Phase_Accumlator
@@ -60,6 +63,11 @@ class Timesim_Config(object):
         self.main_PI = main_PI
         self.has_jitter = has_jitter
 
+        # step input
+        self.step_input_time = step_input_time
+        self.step_frequency = step_frequency
+        self.step_phase = step_phase
+
         # preset
         self.beating_period = 32768
         self.blind_period = 200
diff --git a/src/wrpll_simulation/timesim.py b/src/wrpll_simulation/timesim.py
index 13c4251..50d1368 100644
--- a/src/wrpll_simulation/timesim.py
+++ b/src/wrpll_simulation/timesim.py
@@ -40,6 +40,7 @@ class WRPLL_Timesim(object):
         cfg = self.cfg
 
         timestep_size = cfg.timestep_size
+        step_input_time = self.seconds_to_step(cfg.step_input_time)
         irq_delay = self.seconds_to_step(cfg.irq_delay)
         i2c_comm_delay = self.seconds_to_step(cfg.i2c_comm_delay)
 
@@ -61,6 +62,10 @@ class WRPLL_Timesim(object):
 
         print("Running...")
         for i in range(cfg.sim_length):
+            if i == step_input_time:
+                gtx.set_freq(gtx.freq + cfg.step_frequency)
+                gtx.set_phase(gtx.phase + cfg.step_phase)
+
             if cfg.has_jitter:
                 gtx.update(timestep_size + rng.normal(0, cfg.gtx_jitter))
                 helper.update(timestep_size + rng.normal(0, cfg.dcxo_jitter))