From 203bff205d78b31e2352a876a0c39efaac5dcf8f Mon Sep 17 00:00:00 2001 From: morgan Date: Thu, 11 Jan 2024 17:20:20 +0800 Subject: [PATCH] formatting: add flake8-black py: format using black poetry: add flake8-black flake: add buildInputs for flake8-black --- flake.nix | 5 ++ poetry.lock | 135 ++++++++++++++++++++++++++++- pyproject.toml | 1 + src/wrpll_simulation/sim.py | 144 ++++++++++++++++++++++++------- src/wrpll_simulation/wave_gen.py | 6 +- src/wrpll_simulation/wrpll.py | 43 ++++++--- 6 files changed, 284 insertions(+), 50 deletions(-) diff --git a/flake.nix b/flake.nix index bf930a6..fc52138 100644 --- a/flake.nix +++ b/flake.nix @@ -36,6 +36,11 @@ # fail to build preferWheel = true; }; + flake8-black = super.flake8-black.overridePythonAttrs ( + # ModuleNotFoundError: No module named 'setuptools' + old: { + buildInputs = (old.buildInputs or [ ]) ++ [ super.setuptools ]; + }); }); }; diff --git a/poetry.lock b/poetry.lock index a4a512a..8b074db 100644 --- a/poetry.lock +++ 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system extensions for programs checked with the mypy type checker." +optional = false +python-versions = ">=3.5" +files = [ + {file = "mypy_extensions-1.0.0-py3-none-any.whl", hash = "sha256:4392f6c0eb8a5668a69e23d168ffa70f0be9ccfd32b5cc2d26a34ae5b844552d"}, + {file = "mypy_extensions-1.0.0.tar.gz", hash = "sha256:75dbf8955dc00442a438fc4d0666508a9a97b6bd41aa2f0ffe9d2f2725af0782"}, +] + [[package]] name = "nbclient" version = "0.9.0" @@ -1642,6 +1742,17 @@ files = [ qa = ["flake8 (==3.8.3)", "mypy (==0.782)"] testing = ["docopt", "pytest (<6.0.0)"] +[[package]] +name = "pathspec" +version = "0.12.1" +description = "Utility library for gitignore style pattern matching of file paths." +optional = false +python-versions = ">=3.8" +files = [ + {file = "pathspec-0.12.1-py3-none-any.whl", hash = "sha256:a0d503e138a4c123b27490a4f7beda6a01c6f288df0e4a8b79c7eb0dc7b4cc08"}, + {file = "pathspec-0.12.1.tar.gz", hash = "sha256:a482d51503a1ab33b1c67a6c3813a26953dbdc71c31dacaef9a838c4e29f5712"}, +] + [[package]] name = "pexpect" version = "4.9.0" @@ -1790,6 +1901,17 @@ files = [ [package.extras] tests = ["pytest"] +[[package]] +name = "pycodestyle" +version = "2.11.1" +description = "Python style guide checker" +optional = false +python-versions = ">=3.8" +files = [ + {file = "pycodestyle-2.11.1-py2.py3-none-any.whl", hash = "sha256:44fe31000b2d866f2e41841b18528a505fbd7fef9017b04eff4e2648a0fadc67"}, + {file = "pycodestyle-2.11.1.tar.gz", hash = "sha256:41ba0e7afc9752dfb53ced5489e89f8186be00e599e712660695b7a75ff2663f"}, +] + [[package]] name = "pycparser" version = "2.21" @@ -1801,6 +1923,17 @@ files = [ {file = "pycparser-2.21.tar.gz", hash = "sha256:e644fdec12f7872f86c58ff790da456218b10f863970249516d60a5eaca77206"}, ] +[[package]] +name = "pyflakes" +version = "3.2.0" +description = "passive checker of Python programs" +optional = false +python-versions = ">=3.8" +files = [ + {file = "pyflakes-3.2.0-py2.py3-none-any.whl", hash = "sha256:84b5be138a2dfbb40689ca07e2152deb896a65c3a3e24c251c5c62489568074a"}, + {file = "pyflakes-3.2.0.tar.gz", hash = "sha256:1c61603ff154621fb2a9172037d84dca3500def8c8b630657d1701f026f8af3f"}, +] + [[package]] name = "pygments" version = "2.17.2" @@ -2739,4 +2872,4 @@ testing = ["big-O", "jaraco.functools", "jaraco.itertools", "more-itertools", "p [metadata] lock-version = "2.0" python-versions = "^3.11" -content-hash = "121a69b8179bfa06910de0f2fd41aa135a5a4822061538b5c021ba0641e5fa1a" +content-hash = "2e8cf0f012eb436a406a3d71375e72462cde7ca7669bb85afc9a074b2bae6a2d" diff --git a/pyproject.toml b/pyproject.toml index 2a74d34..8f370ba 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -16,6 +16,7 @@ numba = "^0.58.1" pandas = "^2.1.4" plotly = "^5.18.0" plotly-resampler = "^0.9.1" +flake8-black = "^0.3.6" [build-system] diff --git a/src/wrpll_simulation/sim.py b/src/wrpll_simulation/sim.py index 03c012e..270baca 100644 --- a/src/wrpll_simulation/sim.py +++ b/src/wrpll_simulation/sim.py @@ -26,9 +26,8 @@ def simulation_jit( dcxo_settling_delay, blind_period, start_up_delay, - helper_init_freq=0 + helper_init_freq=0, ): - arr_len = len(time) main = np.zeros(arr_len, dtype=np.int8) @@ -71,7 +70,9 @@ def simulation_jit( if main_pll and not helper_pll: helper_freq = helper_init_freq else: - helper_freq = dcxo_freq * (1 + base_adpll * 0.0001164 / 1_000_000) * ((N-1) / N) + helper_freq = ( + dcxo_freq * (1 + base_adpll * 0.0001164 / 1_000_000) * ((N - 1) / N) + ) main_freq = dcxo_freq * (1 + base_adpll * 0.0001164 / 1_000_000) last_gtx_tag = last_gtx_FF = last_gtx_beat = 0 @@ -106,10 +107,11 @@ def simulation_jit( phase_colr_arm = m_i2c_active = False adpll_max = 8161512 - def clip(n, minn, maxn): return max(min(maxn, n), minn) + + def clip(n, minn, maxn): + return max(min(maxn, n), minn) for i, t in enumerate(time): - h_phase += 360 * helper_freq * (timestep + h_jitter[i]) helper[i] = square(h_phase) @@ -120,27 +122,64 @@ def simulation_jit( gtx[i] = square(gtx_phase) if not last_helper and helper[i]: - gtx_FF, gtx_beating[i] = DDMTD(gtx[i], last_gtx_FF) main_FF, main_beating[i] = DDMTD(main[i], last_main_FF) - gtx_tag, gtx_ready, gtx_blind_counter, gtx_blinded = Deglitcher(gtx_beating[i], gtx_tag, gtx_ready, - gtx_blind_counter, gtx_blinded, blind_period, - last_gtx_beat, last_gtx_tag, counter) + gtx_tag, gtx_ready, gtx_blind_counter, gtx_blinded = Deglitcher( + gtx_beating[i], + gtx_tag, + gtx_ready, + gtx_blind_counter, + gtx_blinded, + blind_period, + last_gtx_beat, + last_gtx_tag, + counter, + ) - main_tag, main_ready, main_blind_counter, main_blinded = Deglitcher(main_beating[i], main_tag, main_ready, - main_blind_counter, main_blinded, blind_period, - last_main_beat, last_main_tag, counter) + main_tag, main_ready, main_blind_counter, main_blinded = Deglitcher( + main_beating[i], + main_tag, + main_ready, + main_blind_counter, + main_blinded, + blind_period, + last_main_beat, + last_main_tag, + counter, + ) - phase_collector_r, wait_gtx, wait_main, colr_gtx_tag, colr_main_tag, phase_collector_state = phase_collector_FSM(gtx_ready, main_ready, gtx_tag, main_tag, - wait_gtx, wait_main, colr_gtx_tag, colr_main_tag, phase_collector_state) + ( + phase_collector_r, + wait_gtx, + wait_main, + colr_gtx_tag, + colr_main_tag, + phase_collector_state, + ) = phase_collector_FSM( + gtx_ready, + main_ready, + gtx_tag, + main_tag, + wait_gtx, + wait_main, + colr_gtx_tag, + colr_main_tag, + phase_collector_state, + ) if phase_collector_r: FW_gtx_tag = colr_gtx_tag FW_main_tag = colr_main_tag - period_collector_r, colr_last_gtx_tag, beating_period, period_collector_state = period_collector_FSM(gtx_ready, gtx_tag, - colr_last_gtx_tag, period_collector_state) + ( + period_collector_r, + colr_last_gtx_tag, + beating_period, + period_collector_state, + ) = period_collector_FSM( + gtx_ready, gtx_tag, colr_last_gtx_tag, period_collector_state + ) counter += 1 @@ -161,14 +200,12 @@ def simulation_jit( main_tag = last_main_tag if i > start_up_delay: - if i % adpll_write_period == 0: period_colr_arm = phase_colr_arm = True # Firmware filters if period_colr_arm and period_collector_r: - period_colr_arm = False period_err = N - beating_period @@ -177,16 +214,19 @@ def simulation_jit( h_integrator += period_err * h_KI h_derivative = (period_err - last_period_err) * h_KD - h_adpll = clip(int(base_adpll + h_prop + h_integrator + h_derivative), -adpll_max, adpll_max) + h_adpll = clip( + int(base_adpll + h_prop + h_integrator + h_derivative), + -adpll_max, + adpll_max, + ) last_period_err = period_err h_i2c_active_index = i h_i2c_active = True if phase_colr_arm and phase_collector_r: - phase_colr_arm = False - tag_diff = ((FW_main_tag - FW_gtx_tag) % N) - if tag_diff > N/2: + tag_diff = (FW_main_tag - FW_gtx_tag) % N + if tag_diff > N / 2: phase_err = tag_diff - N else: phase_err = tag_diff @@ -196,7 +236,11 @@ def simulation_jit( m_integrator += phase_err * m_KI m_derivative = (phase_err - last_phase_err) * m_KD - m_adpll = clip(int(base_adpll + m_prop + m_integrator + m_derivative), -adpll_max, adpll_max) + m_adpll = clip( + int(base_adpll + m_prop + m_integrator + m_derivative), + -adpll_max, + adpll_max, + ) last_phase_err = phase_err m_i2c_active_index = i @@ -204,11 +248,19 @@ def simulation_jit( # i2c communication delay - if h_i2c_active and i >= i2c_comm_delay + dcxo_settling_delay + h_i2c_active_index: - helper_freq = dcxo_freq * (1 + h_adpll * 0.0001164 / 1_000_000) * ((N-1) / N) + if ( + h_i2c_active + and i >= i2c_comm_delay + dcxo_settling_delay + h_i2c_active_index + ): + helper_freq = ( + dcxo_freq * (1 + h_adpll * 0.0001164 / 1_000_000) * ((N - 1) / N) + ) h_i2c_active = False - if m_i2c_active and i >= i2c_comm_delay + dcxo_settling_delay + m_i2c_active_index: + if ( + m_i2c_active + and i >= i2c_comm_delay + dcxo_settling_delay + m_i2c_active_index + ): main_freq = dcxo_freq * (1 + m_adpll * 0.0001164 / 1_000_000) m_i2c_active = False @@ -222,7 +274,19 @@ def simulation_jit( helperfreq[i] = helper_freq mainfreq[i] = main_freq - return period_err_arr, phase_err_arr, helper_adpll_arr, main_adpll_arr, gtx_beating, main_beating, gtx, helper, main, helperfreq, mainfreq + return ( + period_err_arr, + phase_err_arr, + helper_adpll_arr, + main_adpll_arr, + gtx_beating, + main_beating, + gtx, + helper, + main, + helperfreq, + mainfreq, + ) @njit @@ -231,8 +295,17 @@ def DDMTD(sig_in, last_FF): @njit -def Deglitcher(beating, t_out, t_ready, blind_counter, blinded, blind_period, last_beat, last_tag, counter): - +def Deglitcher( + beating, + t_out, + t_ready, + blind_counter, + blinded, + blind_period, + last_beat, + last_tag, + counter, +): if blind_counter == 0 and beating and not last_beat: # rising t_out = counter t_ready = 1 @@ -251,8 +324,17 @@ def Deglitcher(beating, t_out, t_ready, blind_counter, blinded, blind_period, la @njit -def phase_collector_FSM(g_tag_r, m_tag_r, gtx_tag, main_tag, wait_gtx, wait_main, colr_gtx_tag, colr_main_tag, FSM_state): - +def phase_collector_FSM( + g_tag_r, + m_tag_r, + gtx_tag, + main_tag, + wait_gtx, + wait_main, + colr_gtx_tag, + colr_main_tag, + FSM_state, +): collector_r = 0 match FSM_state: diff --git a/src/wrpll_simulation/wave_gen.py b/src/wrpll_simulation/wave_gen.py index a0db5e7..aa30f18 100644 --- a/src/wrpll_simulation/wave_gen.py +++ b/src/wrpll_simulation/wave_gen.py @@ -1,11 +1,9 @@ import numpy as np -import numba as nb from numba import njit - def gussian_jitter(RMS_jitter, size, seed=None): - return np.random.default_rng(seed).normal(0, RMS_jitter/2, size) + return np.random.default_rng(seed).normal(0, RMS_jitter / 2, size) @njit(fastmath=True) @@ -14,7 +12,7 @@ def square_with_jitter(time, freq, jitter): wave = np.empty(n) timestep = time[1] - time[0] - phase = 0. + phase = 0.0 for i in range(n): phase += 360 * freq * (timestep + jitter[i]) wave[i] = square(phase) diff --git a/src/wrpll_simulation/wrpll.py b/src/wrpll_simulation/wrpll.py index 4c1dea5..9a2cfe0 100644 --- a/src/wrpll_simulation/wrpll.py +++ b/src/wrpll_simulation/wrpll.py @@ -3,8 +3,7 @@ from wrpll_simulation.sim import simulation_jit from wrpll_simulation.wave_gen import gussian_jitter -class WRPLL_simulator(): - +class WRPLL_simulator: def __init__( self, timestep, @@ -24,10 +23,9 @@ class WRPLL_simulator(): N=4069, blind_period=128, helper_init_freq=None, - seed=None + seed=None, ): - - self.time = np.linspace(0, timestep*total_steps, total_steps) + self.time = np.linspace(0, timestep * total_steps, total_steps) self.sim_mode = sim_mode self.h_KP = helper_filter["KP"] self.h_KI = helper_filter["KI"] @@ -47,16 +45,21 @@ class WRPLL_simulator(): self.helper_init_freq = helper_init_freq # freq_acquisition() error - freq_diff = gtx_freq - dcxo_freq + \ - np.random.default_rng(seed).uniform(-freq_acquisition_error, freq_acquisition_error) + freq_diff = ( + gtx_freq + - dcxo_freq + + np.random.default_rng(seed).uniform( + -freq_acquisition_error, freq_acquisition_error + ) + ) self.base_adpll = int(freq_diff * (1 / dcxo_freq) * (1e6 / 0.0001164)) # sim config - self.i2c_comm_delay = int(i2c_comm_delay/timestep) - self.dcxo_settling_delay = int(dcxo_settling_delay/timestep) + self.i2c_comm_delay = int(i2c_comm_delay / timestep) + self.dcxo_settling_delay = int(dcxo_settling_delay / timestep) self.blind_period = blind_period - self.adpll_write_period = int(adpll_write_period/timestep) - self.start_up_delay = int(start_up_delay/timestep) + self.adpll_write_period = int(adpll_write_period / timestep) + self.start_up_delay = int(start_up_delay / timestep) if type(self.sim_mode) is not str: raise ValueError(f"pll_type {type(self.sim_mode)} is not a string") @@ -67,7 +70,7 @@ class WRPLL_simulator(): elif self.sim_mode.lower() == "helper_pll": self.helper_pll = True elif self.sim_mode.lower() == "main_pll": - if self.helper_init_freq == None: + if self.helper_init_freq is None: raise ValueError("main pll mode need to set a helper frequency") self.main_pll = True else: @@ -75,7 +78,19 @@ class WRPLL_simulator(): def run(self): print("running simulation...") - self.period_err, self.phase_err, self.helper_adpll, self.main_adpll, self.gtx_beating, self.main_beating, self.gtx, self.helper, self.main, self.helperfreq, self.mainfreq = simulation_jit( + ( + self.period_err, + self.phase_err, + self.helper_adpll, + self.main_adpll, + self.gtx_beating, + self.main_beating, + self.gtx, + self.helper, + self.main, + self.helperfreq, + self.mainfreq, + ) = simulation_jit( self.time, self.gtx_freq, self.gtx_jitter, @@ -97,6 +112,6 @@ class WRPLL_simulator(): self.dcxo_settling_delay, self.blind_period, self.start_up_delay, - self.helper_init_freq + self.helper_init_freq, ) print("Done!")