fix helper PLL glitches
sim: rename collector to phase_collector sim: add period_collector for gtx tags sim: trigger helper PLL after period_collector_r sim: remove cycle slip compensation sim: generator gtx in time loop wave_gen: replace square generator with phase accumulator wave_gen&wrpll: add white_noise generator docs: remove section & png about cycle slipping and deglitcher failure
This commit is contained in:
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17
README.md
17
README.md
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@ -49,20 +49,3 @@ source .venv/bin/activate
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## Limitation
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As the simulation is not cycle nor delay accurate, there will be more glitches than the hardware implementation
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### Helper PLL glitches (remedies are added to follow hardware behavior)
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- Cycle slipping issue will appear as $|\Delta{period}| \sim N$
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- During hardware testing, slipping issue is not common
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- It's recommended to turn cycle_slip_comp ON to reduce slipping and have a more accurate simulation
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- Deglitcher fail issue will appear as $|\Delta{period}| \sim N/2$
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- There are no such issue for hardware
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- It's recommended to set blind_period higher than the hardware setting (around 300 is sufficient)
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141
src/sim.py
141
src/sim.py
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@ -6,7 +6,8 @@ from wave_gen import square
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@njit
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def simulation_jit(
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time,
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gtx,
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gtx_freq,
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gtx_jitter,
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helper_pll,
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main_pll,
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h_KP,
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@ -16,13 +17,13 @@ def simulation_jit(
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m_KI,
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m_KD,
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dcxo_freq,
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dcxo_jitter_SD,
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h_jitter,
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m_jitter,
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base_adpll,
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N,
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adpll_write_period,
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blind_period,
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start_up_delay,
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cycle_slip_comp=True,
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helper_init_freq=0
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):
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@ -30,6 +31,7 @@ def simulation_jit(
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main = np.zeros(arr_len, dtype=np.int8)
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helper = np.zeros(arr_len, dtype=np.int8)
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gtx = np.zeros(arr_len, dtype=np.int8)
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gtx_tag = 0
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gtx_ready = 0
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@ -40,7 +42,6 @@ def simulation_jit(
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main_ready = 0
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main_FF = 0
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main_beating = np.zeros(arr_len, dtype=np.int8)
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collector_r = 0
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phase_err_arr = np.zeros(arr_len, dtype=np.int16)
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period_err_arr = np.zeros(arr_len, dtype=np.int16)
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@ -50,15 +51,20 @@ def simulation_jit(
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helperfreq = np.zeros(arr_len, dtype=np.int32)
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mainfreq = np.zeros(arr_len, dtype=np.int32)
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# initial condition
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main_init_offset = (np.random.uniform(0, 360)) / (360 * dcxo_freq)
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helper_init_offset = (np.random.uniform(0, 360)) / (360 * dcxo_freq)
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phase_collector_r = 0
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colr_gtx_tag = colr_main_tag = 0
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phase_collector_state = 0
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# intermediate values
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helper_jitter = np.random.normal(0, dcxo_jitter_SD)
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main_jitter = np.random.normal(0, dcxo_jitter_SD)
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helper_cycle_num = 0
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main_cycle_num = 0
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period_collector_r = 0
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colr_last_gtx_tag = 0
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beating_period = 0
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period_collector_state = 0
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# initial condition
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timestep = time[1] - time[0]
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gtx_phase = 0
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h_phase = np.random.uniform(0, 360)
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m_phase = np.random.uniform(0, 360)
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if main_pll and not helper_pll:
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helper_freq = helper_init_freq
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@ -66,12 +72,10 @@ def simulation_jit(
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helper_freq = dcxo_freq * (1 + base_adpll * 0.0001164 / 1_000_000) * ((N-1) / N)
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main_freq = dcxo_freq * (1 + base_adpll * 0.0001164 / 1_000_000)
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FSM_state = 0
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coll_gtx_tag = coll_main_tag = 0
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last_gtx_tag = last_gtx_FF = last_gtx_beat = 0
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last_main_tag = last_main_FF = last_main_beat = 0
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last_helper = last_main = 0
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last_helper = 0
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counter = 0
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gtx_blind_counter = 0
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@ -84,38 +88,32 @@ def simulation_jit(
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wait_main = True
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# firmware values
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FW_gtx_tag = FW_last_gtx_tag = 0
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FW_gtx_tag = 0
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FW_main_tag = 0
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period_err = last_period_err = 0
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h_prop = h_integrator = h_derivative = 0
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h_adpll = base_adpll
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h_i2c_active = False
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period_colr_arm = h_i2c_active = False
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phase_err = last_phase_err = 0
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m_prop = m_integrator = m_derivative = 0
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m_adpll = base_adpll
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m_i2c_active = False
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phase_colr_arm = m_i2c_active = False
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adpll_active = False
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adpll_max = 8161512
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def clip(n, minn, maxn): return max(min(maxn, n), minn)
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for i, t in enumerate(time):
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helper[i], helper_cycle_num, helper_jitter = square(
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t + helper_init_offset, helper_freq, dcxo_jitter_SD, helper_jitter, helper_cycle_num)
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main[i], main_cycle_num, main_jitter = square(
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t + main_init_offset, main_freq, dcxo_jitter_SD, main_jitter, main_cycle_num)
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h_phase += 360 * helper_freq * (timestep + h_jitter[i])
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helper[i] = square(h_phase)
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# continuous glitchless output, assume very small frequency change
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if h_i2c_active and helper[i]:
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helper_freq = dcxo_freq * (1 + h_adpll * 0.0001164 / 1_000_000) * ((N-1) / N)
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h_i2c_active = False
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m_phase += 360 * main_freq * (timestep + m_jitter[i])
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main[i] = square(m_phase)
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if m_i2c_active and main[i]:
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main_freq = dcxo_freq * (1 + m_adpll * 0.0001164 / 1_000_000)
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m_i2c_active = False
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gtx_phase += 360 * gtx_freq * (timestep + gtx_jitter[i])
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gtx[i] = square(gtx_phase)
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if not last_helper and helper[i]:
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@ -130,12 +128,15 @@ def simulation_jit(
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main_blind_counter, main_blinded, blind_period,
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last_main_beat, last_main_tag, counter)
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collector_r, wait_gtx, wait_main, coll_gtx_tag, coll_main_tag, FSM_state = Collector_FSM(gtx_ready, main_ready, gtx_tag, main_tag,
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wait_gtx, wait_main, coll_gtx_tag, coll_main_tag, FSM_state)
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phase_collector_r, wait_gtx, wait_main, colr_gtx_tag, colr_main_tag, phase_collector_state = phase_collector_FSM(gtx_ready, main_ready, gtx_tag, main_tag,
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wait_gtx, wait_main, colr_gtx_tag, colr_main_tag, phase_collector_state)
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if collector_r:
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FW_gtx_tag = coll_gtx_tag
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FW_main_tag = coll_main_tag
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if phase_collector_r:
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FW_gtx_tag = colr_gtx_tag
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FW_main_tag = colr_main_tag
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period_collector_r, colr_last_gtx_tag, beating_period, period_collector_state = period_collector_FSM(gtx_ready, gtx_tag,
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colr_last_gtx_tag, period_collector_state)
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counter += 1
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@ -158,20 +159,11 @@ def simulation_jit(
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if i > start_up_delay:
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# Firmware filters
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if adpll_active and collector_r:
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if cycle_slip_comp:
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period = FW_gtx_tag - FW_last_gtx_tag
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if period > 3 * N/2:
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period = period - N
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period_err = N - period
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else:
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period_err = (N - (FW_gtx_tag - FW_last_gtx_tag))
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tag_diff = ((FW_main_tag - FW_gtx_tag) % N)
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if tag_diff > N/2:
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phase_err = tag_diff - N
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else:
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phase_err = tag_diff
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if period_colr_arm and period_collector_r:
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period_colr_arm = False
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period_err = N - beating_period
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if helper_pll:
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h_prop = period_err * h_KP
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@ -180,8 +172,18 @@ def simulation_jit(
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h_adpll = clip(int(base_adpll + h_prop + h_integrator + h_derivative), -adpll_max, adpll_max)
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last_period_err = period_err
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helper_freq = dcxo_freq * (1 + h_adpll * 0.0001164 / 1_000_000) * ((N-1) / N)
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h_i2c_active = True
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if phase_colr_arm and phase_collector_r:
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phase_colr_arm = False
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tag_diff = ((FW_main_tag - FW_gtx_tag) % N)
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if tag_diff > N/2:
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phase_err = tag_diff - N
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else:
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phase_err = tag_diff
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if main_pll:
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m_prop = phase_err * m_KP
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m_integrator += phase_err * m_KI
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@ -189,16 +191,13 @@ def simulation_jit(
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m_adpll = clip(int(base_adpll + m_prop + m_integrator + m_derivative), -adpll_max, adpll_max)
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last_phase_err = phase_err
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main_freq = dcxo_freq * (1 + m_adpll * 0.0001164 / 1_000_000)
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m_i2c_active = True
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adpll_active = False
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if i % adpll_write_period == 0:
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adpll_active = True
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FW_last_gtx_tag = FW_gtx_tag
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period_colr_arm = phase_colr_arm = True
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last_helper = helper[i]
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last_main = main[i]
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# Data
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period_err_arr[i] = period_err
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@ -208,7 +207,7 @@ def simulation_jit(
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helperfreq[i] = helper_freq
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mainfreq[i] = main_freq
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return period_err_arr, phase_err_arr, helper_adpll_arr, main_adpll_arr, gtx_beating, main_beating, helper, main, helperfreq, mainfreq
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return period_err_arr, phase_err_arr, helper_adpll_arr, main_adpll_arr, gtx_beating, main_beating, gtx, helper, main, helperfreq, mainfreq
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@njit
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@ -237,37 +236,55 @@ def Deglitcher(beating, t_out, t_ready, blind_counter, blinded, blind_period, la
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@njit
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def Collector_FSM(g_tag_r, m_tag_r, gtx_tag, main_tag, wait_gtx, wait_main, coll_gtx_tag, coll_main_tag, FSM_state):
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def phase_collector_FSM(g_tag_r, m_tag_r, gtx_tag, main_tag, wait_gtx, wait_main, colr_gtx_tag, colr_main_tag, FSM_state):
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collector_r = 0
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match FSM_state:
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case 0: # IDEL
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if g_tag_r and m_tag_r:
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coll_gtx_tag = gtx_tag
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coll_main_tag = main_tag
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colr_gtx_tag = gtx_tag
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colr_main_tag = main_tag
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FSM_state = 3 # OUTPUT
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elif g_tag_r:
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coll_gtx_tag = gtx_tag
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colr_gtx_tag = gtx_tag
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wait_main = True
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FSM_state = 2 # WAITMAIN
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elif m_tag_r:
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coll_main_tag = main_tag
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colr_main_tag = main_tag
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wait_gtx = True
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FSM_state = 1 # WAITGTX
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case 1: # WAITGTX
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if g_tag_r:
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coll_gtx_tag = gtx_tag
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colr_gtx_tag = gtx_tag
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FSM_state = 3 # OUTPUT
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case 2: # WAITMAIN
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if m_tag_r:
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coll_main_tag = main_tag
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colr_main_tag = main_tag
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FSM_state = 3 # OUTPUT
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case 3: # OUTPUT
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wait_gtx = wait_main = False
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collector_r = 1
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FSM_state = 0
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return collector_r, wait_gtx, wait_main, coll_gtx_tag, coll_main_tag, FSM_state
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return collector_r, wait_gtx, wait_main, colr_gtx_tag, colr_main_tag, FSM_state
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@njit
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def period_collector_FSM(g_tag_r, gtx_tag, colr_last_gtx_tag, FSM_state):
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collector_r = 0
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beating_period = 0
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match FSM_state:
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case 0: # IDEL
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if g_tag_r:
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colr_last_gtx_tag = gtx_tag
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FSM_state = 1
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case 1: # OUTPUT
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if g_tag_r:
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beating_period = gtx_tag - colr_last_gtx_tag
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collector_r = 1
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FSM_state = 0 # IDEL
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return collector_r, colr_last_gtx_tag, beating_period, FSM_state
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@ -1,69 +1,28 @@
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import numpy as np
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import numba as nb
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from numba import njit
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@njit
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def square(time, freq, jitter_SD, jitter, cycle_num):
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"""
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A scipy like square wave with jitter
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Parameters
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----------
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time : timestamp, in seconds
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freq : frequency in Hz
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jitter_SD : standard deviation of jitter, in seconds
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jitter : gaussian noise with `jitter_SD` as its standard deviation
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cycle_num : time // period = cycle_num
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----------
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"""
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period = 1/(freq)
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quarter = (period / 4)
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out = 0
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# A T/4 shift is applied to the following to match scipy square fn
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# ┌──────┐
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# ───┘ └────
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# T/4 3T/4
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nth_cycle, t = np.divmod(time + period / 4, period)
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if t >= (quarter + jitter) and t <= (3*quarter + jitter):
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out = 1
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else:
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out = 0
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# update jitter every cycle
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if nth_cycle != cycle_num:
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jitter = np.random.normal(0, jitter_SD)
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cycle_num = nth_cycle
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return out, cycle_num, jitter
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def white_noise(low, high, size, seed=None):
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return np.random.default_rng(seed).uniform(low, high, size)
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@njit
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def square_arr(time, freq, jitter_SD):
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"""
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A scipy like square wave with jitter
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Parameters
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----------
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time : numpy array
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freq : frequency in Hz
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jitter_SD : standard deviation of jitter, in seconds
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----------
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"""
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wave = np.zeros(len(time))
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jitter = np.random.normal(0, jitter_SD)
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cycle_num = 0
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for i, t in enumerate(time):
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wave[i], cycle_num, jitter = square(t, freq, jitter_SD, jitter, cycle_num)
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@njit(fastmath=True)
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def square_with_jitter(time, freq, jitter):
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n = len(time)
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wave = np.empty(n)
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timestep = time[1] - time[0]
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phase = 0.
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for i in range(n):
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phase += 360 * freq * (timestep + jitter[i])
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wave[i] = square(phase)
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return wave
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@njit
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def square(x):
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if np.mod(x, 360) < 180:
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return 0
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else:
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return 1
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28
src/wrpll.py
28
src/wrpll.py
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@ -1,5 +1,5 @@
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import numpy as np
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from wave_gen import square_arr
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from wave_gen import white_noise
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from sim import simulation_jit
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@ -12,16 +12,16 @@ class WRPLL_simulator():
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helper_filter,
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main_filter,
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gtx_freq,
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gtx_jitter_SD,
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gtx_jitter,
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dcxo_freq,
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dcxo_jitter_SD,
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dcxo_jitter,
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freq_acquisition_SD,
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N,
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adpll_write_period,
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blind_period,
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start_up_delay,
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cycle_slip_comp,
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helper_init_freq=None
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helper_init_freq=None,
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seed=None
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):
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self.time = time
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@ -34,13 +34,15 @@ class WRPLL_simulator():
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self.m_KD = main_filter["KD"]
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# init condition
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self.gtx_freq = gtx_freq
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self.gtx_jitter = white_noise(-gtx_jitter, gtx_jitter, len(time), seed)
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self.dcxo_freq = dcxo_freq
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||||
self.dcxo_jitter_SD = dcxo_jitter_SD
|
||||
self.h_jitter = white_noise(-dcxo_jitter, dcxo_jitter, len(time), seed)
|
||||
self.m_jitter = white_noise(-dcxo_jitter, dcxo_jitter, len(time), seed)
|
||||
self.N = N
|
||||
self.helper_init_freq = helper_init_freq
|
||||
|
||||
self.gtx = square_arr(time, gtx_freq, gtx_jitter_SD)
|
||||
|
||||
# freq_acquisition() error
|
||||
freq_diff = gtx_freq - dcxo_freq + np.random.normal(0, freq_acquisition_SD)
|
||||
self.base_adpll = int(freq_diff * (1 / dcxo_freq) * (1e6 / 0.0001164))
|
||||
|
|
@ -49,7 +51,6 @@ class WRPLL_simulator():
|
|||
self.adpll_write_period = adpll_write_period
|
||||
self.blind_period = blind_period
|
||||
self.start_up_delay = start_up_delay
|
||||
self.cycle_slip_comp = cycle_slip_comp
|
||||
|
||||
if type(self.sim_mode) is not str:
|
||||
raise ValueError(f"pll_type {type(self.sim_mode)} is not a string")
|
||||
|
|
@ -68,9 +69,10 @@ class WRPLL_simulator():
|
|||
|
||||
def run(self):
|
||||
print("running simulation...")
|
||||
self.period_err, self.phase_err, self.helper_adpll, self.main_adpll, self.gtx_beating, self.main_beating, self.helper, self.main, self.helperfreq, self.mainfreq = simulation_jit(
|
||||
self.period_err, self.phase_err, self.helper_adpll, self.main_adpll, self.gtx_beating, self.main_beating, self.gtx, self.helper, self.main, self.helperfreq, self.mainfreq = simulation_jit(
|
||||
self.time,
|
||||
self.gtx,
|
||||
self.gtx_freq,
|
||||
self.gtx_jitter,
|
||||
self.helper_pll,
|
||||
self.main_pll,
|
||||
self.h_KP,
|
||||
|
|
@ -80,13 +82,13 @@ class WRPLL_simulator():
|
|||
self.m_KI,
|
||||
self.m_KD,
|
||||
self.dcxo_freq,
|
||||
self.dcxo_jitter_SD,
|
||||
self.h_jitter,
|
||||
self.m_jitter,
|
||||
self.base_adpll,
|
||||
self.N,
|
||||
self.adpll_write_period,
|
||||
self.blind_period,
|
||||
self.start_up_delay,
|
||||
self.cycle_slip_comp,
|
||||
self.helper_init_freq
|
||||
)
|
||||
print("Done!")
|
||||
|
|
|
|||
Loading…
Reference in New Issue