128 lines
4.7 KiB
Python
128 lines
4.7 KiB
Python
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import typing as tp
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import numpy as np
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from numba.core.types import *
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from numba.experimental import jitclass
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from wrpll_simulation.config import Timesim_Config
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from wrpll_simulation.timesim_node import *
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@jitclass
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class WRPLL_Timesim(object):
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cfg: Timesim_Config
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time: float32[:]
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freq_diff: float32[:]
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phase_diff: float32[:]
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helper_error: int16[:]
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main_error: int16[:]
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def __init__(self, cfg: Timesim_Config, rng: tp.Generator):
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# subclass/inheritance is not supported by numba jitclass
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# https://github.com/numba/numba/issues/1694
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self.cfg = cfg
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sim_length = cfg.sim_length
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stop_time = cfg.timestep_size * sim_length
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self.time = np.linspace(0, stop_time, sim_length).astype(np.float32)
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self.freq_diff = np.zeros(sim_length, dtype=np.float32)
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self.phase_diff = np.zeros(sim_length, dtype=np.float32)
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self.helper_error = np.zeros(sim_length, dtype=np.int16)
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self.main_error = np.zeros(sim_length, dtype=np.int16)
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# __post_init__ is not supported by numba jitclass
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# https://github.com/numba/numba/issues/4037
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self.simulate(rng)
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def simulate(self, rng: tp.Generator):
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cfg = self.cfg
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timestep_size = cfg.timestep_size
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irq_delay = self.seconds_to_step(cfg.irq_delay)
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i2c_comm_delay = self.seconds_to_step(cfg.i2c_comm_delay)
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# simulation node
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gtx = Phase_Accumlator(cfg.gtx_init_freq, cfg.gtx_init_phase)
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helper = Phase_Accumlator(cfg.helper_init_freq, cfg.helper_init_phase)
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main = Phase_Accumlator(cfg.main_init_freq, cfg.main_init_phase)
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ddmtd_gtx = DDMTD(cfg.blind_period)
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ddmtd_main = DDMTD(cfg.blind_period)
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gtx_tag_irq = EventManager_IRQ()
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main_tag_irq = EventManager_IRQ()
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tag_collector = Tag_Collector(cfg.beating_period)
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helper_PLL = PI_loop(cfg.helper_PI, cfg.helper_init_freq, 0, cfg.adpll_limit)
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main_PLL = PI_loop(cfg.main_PI, cfg.main_init_freq, 0, cfg.adpll_limit)
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counter = 0
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print("Running...")
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for i in range(cfg.sim_length):
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if cfg.has_jitter:
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gtx.update(timestep_size + rng.normal(0, cfg.gtx_jitter))
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helper.update(timestep_size + rng.normal(0, cfg.dcxo_jitter))
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main.update(timestep_size + rng.normal(0, cfg.dcxo_jitter))
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else:
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gtx.update(timestep_size)
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helper.update(timestep_size)
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main.update(timestep_size)
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# GATEWARE
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if helper.is_rising():
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ddmtd_gtx.sync_update(gtx.o, counter)
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ddmtd_main.sync_update(main.o, counter)
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# for clock domain crossing
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gtx_tag_irq.multireg(ddmtd_gtx.tag_ready, ddmtd_gtx.tag)
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main_tag_irq.multireg(ddmtd_main.tag_ready, ddmtd_main.tag)
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counter += 1
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if main.is_rising():
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# Generate interrupt request
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gtx_tag_irq.sync_update(i)
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main_tag_irq.sync_update(i)
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# FIRMWARE
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if gtx_tag_irq.is_due(i, irq_delay):
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tag_collector.collect_gtx_tag(gtx_tag_irq.tag_csr)
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helper_PLL.update(i, tag_collector.get_period_error())
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if tag_collector.is_phase_error_ready():
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tag_collector.set_phase_error_ready(False)
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main_PLL.update(i, tag_collector.get_phase_error())
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if main_tag_irq.is_due(i, irq_delay):
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tag_collector.collect_main_tag(main_tag_irq.tag_csr)
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if tag_collector.is_phase_error_ready():
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tag_collector.set_phase_error_ready(False)
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main_PLL.update(i, tag_collector.get_phase_error())
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if helper_PLL.i2c_is_due(i, i2c_comm_delay):
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helper.set_freq(helper_PLL.get_new_freq())
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if main_PLL.i2c_is_due(i, i2c_comm_delay):
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main.set_freq(main_PLL.get_new_freq())
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# Data Logging
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self.freq_diff[i] = np.float32(main.freq - gtx.freq)
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self.phase_diff[i] = np.float32((main.phase - gtx.phase) % 360)
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if self.phase_diff[i] > 180:
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self.phase_diff[i] -= 360
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if helper_PLL.i2c_is_due(i, i2c_comm_delay):
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self.helper_error[i] = tag_collector.get_period_error()
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elif i > 0:
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self.helper_error[i] = self.helper_error[i - 1]
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if main_PLL.i2c_is_due(i, i2c_comm_delay):
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self.main_error[i] = tag_collector.get_phase_error()
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elif i > 0:
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self.main_error[i] = self.main_error[i - 1]
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def seconds_to_step(self, seconds: float64):
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return int(seconds / self.cfg.timestep_size)
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